Search results for "Cliff C. N. Sze"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze	Postgrid Clock Routing for High Performance Microprocessor Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert	WRIP: logic restructuring techniques for wirelength-driven incremental placement.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov	Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	systems on chips, physical synthesis
1	Joshua Friedrich, Ruchir Puri, U. Brandt, M. Buehler, Jack DiLullo, J. Hopkins, M. Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, D. Lamb, A. Lee, F. Musante, J. Noack, Peter J. Osler, S. Posluszny, H. Qian, S. Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, B. R. Russell, Cliff C. N. Sze, Gustavo E. Téllez	Design methodology for the IBM POWER7 microprocessor.	IBM Journal of Research and Development	2011	DBLP DOI BibTeX RDF
1	Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy	The ISPD-2011 routability-driven placement contest and benchmark suite.	ISPD	2011	DBLP DOI BibTeX RDF
1	Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze	Grid-to-ports clock routing for high performance microprocessor designs.	ISPD	2011	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze	The future of clock network synthesis.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan	Shedding Physical Synthesis Area Bloat.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.	Quantifying academic placer performance on custom designs.	ISPD	2011	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
1	Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
1	Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
1	Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz	The ISPD global routing benchmark suite.	ISPD	2008	DBLP DOI BibTeX RDF	benchmarks, physical design, VLSI routing
1	Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz	The nuts and bolts of physical synthesis.	SLIP	2007	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze	Accurate estimation of global buffer delay within a floorplan.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang	Timing-driven Steiner trees are (practically) free.	DAC	2006	DBLP DOI BibTeX RDF	arborescence, timing-driven, rectilinear Steiner tree
1	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze	Fast algorithms for slew constrained minimum cost buffering.	DAC	2006	DBLP DOI BibTeX RDF	slew constraint, physical design, buffer insertion
1	Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze	Integrated placement and skew optimization for rotary clocking.	DATE	2006	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
1	Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path based buffer insertion.	DAC	2005	DBLP DOI BibTeX RDF	layout, physical design, global routing, buffer insertion, power minimization, interconnect synthesis
1	Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Making fast buffer insertion even faster via approximation techniques.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Register placement for low power clock network.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu	Skew scheduling and clock routing for improved tolerance to process variations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	layout embedding, skew scheduling, reliability, process variation, clock routing
1	Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze	Porosity-aware buffered Steiner tree construction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang	Multilevel circuit clustering for delay minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze, Jiang Hu, Charles J. Alpert	A place and route aware buffered Steiner tree construction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze	Accurate estimation of global buffer delay within a floorplan.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering for delay minimization under a more general delay model.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze, Ting-Chi Wang	Multi-Level Circuit Clustering for Delay Minimization.	IWLS	2002	DBLP BibTeX RDF
1	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering with variable interconnect delay.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Chin Ngai Sze, Yu-Liang Wu	Improved alternative wiring scheme applying dominator relationship.	ASP-DAC	2001	DBLP DOI BibTeX RDF

Publications of Cliff C. N. Sze Chin Ngai Sze Cliff N. Sze ( http://dblp.L3S.de/Authors/Cliff_C._N._Sze )