Search results for "Cristinel Ababei"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Rajendra S. Katti, Cristinel Ababei	Secure Comparison Without Explicit XOR	CoRR	2012	DBLP BibTeX RDF
1	Cristinel Ababei, Hamed Sajjadi Kia, Om Prakash Yadav, Jingcao Hu	Energy and reliability oriented mapping for regular Networks-on-Chip.	NOCS	2011	DBLP BibTeX RDF
1	Hamed Sajjadi Kia, Cristinel Ababei	A new fault-tolerant and congestion-aware adaptive routing algorithm for regular Networks-on-Chip.	IEEE Congress on Evolutionary Computation	2011	DBLP DOI BibTeX RDF
1	Hamed Sajjadi Kia, Cristinel Ababei	Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Vitor de Paulo, Cristinel Ababei	3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans.	Int. J. Reconfig. Comp.	2010	DBLP DOI BibTeX RDF
1	Cristinel Ababei	Network on chip design and optimization using specialized influence models.	DAC	2010	DBLP DOI BibTeX RDF	VFI design style, optimization, network on chip, influence model
1	Cristinel Ababei	Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Cristinel Ababei	Speeding Up FPGA Placement via Partitioning and Multithreading.	Int. J. Reconfig. Comp.	2009	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Rajendra S. Katti	Achieving network on chip fault tolerance by adaptive remapping.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Cristinel Ababei	Parallel placement for FPGAs revisited.	FPGA	2009	DBLP DOI BibTeX RDF	fpga placement, multithreading, parallel simulated annealing
1	Vitor de Paulo, Cristinel Ababei	A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans.	ReConFig	2009	DBLP DOI BibTeX RDF	Homogeneous Network-on-Chip, heterogeneous floorplan, 3D circuits
1	Cristinel Ababei, Kia Bazargan	Non-contiguous linear placement for reconfigurable fabrics.	IJES	2006	DBLP DOI BibTeX RDF
1	Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh	Statistical Analysis and Design of HARP FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	Three-dimensional place and route for FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Timing-driven partitioning-based placement for island style FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar	Placement and Routing in 3D Integrated Circuits.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	VLSI, Placement and routing
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	Three-dimensional place and route for FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh	HARP: hard-wired routing pattern FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	3D FPGAs: placement, routing, and architecture evaluation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Pongstorn Maidee, Kia Bazargan	Exploring Potential Benefits of 3D FPGA Integration.	FPL	2004	DBLP DOI BibTeX RDF
1	Cristinel Ababei	TPR: Three-D Place and Route for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Non-Contiguous Linear Placement for Reconfigurable Fabrics.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
1	Cristinel Ababei, Kia Bazargan	Timing Minimization by Statistical Timing hMetis-based Partitioning.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Placement Method Targeting Predictability Robustness and Performance.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Statistical Timing Driven Partitioning for VLSI Circuits.	DATE	2002	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis	Multi-objective circuit partitioning for cutsize and path-based delay minimization.	ICCAD	2002	DBLP DOI BibTeX RDF

Publications of "Cristinel Ababei" ( http://dblp.L3S.de/Authors/Cristinel_Ababei )