Search results for "DMA controller"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch	An Enhanced DMA Controller in SIMD Processors for Video Applications.	ARCS	2009	DBLP DOI BibTeX RDF
2	Sufian Sudeng, Arthit Thongtak	Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	asynchronous control circuits, asynchronous DMA controller, template based technique, logic synthesis, Signal Transition Graph (STG)
2	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
2	Tai-Yi Huang, Jane W.-S. Liu, David Hull	A Method for Bounding the Effect of DMA I/O Interference on Program Execution Time. (PDF / PS)	IEEE Real-Time Systems Symposium	1996	DBLP DOI BibTeX RDF	DMA I/O operation, program execution time, DMA controller, cycle-stealing mode, bus cycles, cycle stealing operation, executing program, machine instruction, instruction-cache architectures, input output operation, simulations, real-time systems, worst-case execution time, data transfer
1	Nikola Vujic, Lluc Alvarez, Marc González, Xavier Martorell, Eduard Ayguadé	DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memories.	Conf. Computing Frontiers	2012	DBLP DOI BibTeX RDF
1	A. Wadekar, S. Swapnil, R. B. Lohani	Design and implementation of a universal DMA controller.	ICWET	2011	DBLP DOI BibTeX RDF
1	David Szczesny, Sebastian Hessel, Shadi Traboulsi, Attila Bilgic	Optimizing the Processing Performance of a Smart DMA Controller for LTE Terminals.	RTCSA	2010	DBLP DOI BibTeX RDF
1	Sebastian Hessel, David Szczesny, Felix Bruns, Attila Bilgic, Josef Hausner	Architectural Analysis of a Smart DMA Controller for Protocol Stack Acceleration in LTE Terminals.	VTC Fall	2010	DBLP DOI BibTeX RDF
1	Chia-Hao Yu, Chung-Kai Liu, Chih-Heng Kang, Tsun-Hsien Wang, Chih-Chien Shen, Shau-Yin Tseng	An Efficient DMA Controller for Multimedia Application in MPU Based SOC.	ICME	2007	DBLP DOI BibTeX RDF
1	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	embedded systems, power-aware, external memory, media processor, bus arbitration
1	Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu	Design and test of a scalable security processor.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	3D FPGAs: placement, routing, and architecture evaluation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Chul Kim, A. M. Rassau, Mike Myung-Ok Lee	3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	HiPEAC	2005	DBLP DOI BibTeX RDF	embedded systems, Power-aware, external memory, media processor, bus arbitration
1	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
1	Mattias O'Nils, Axel Jantsch	Device Driver and DMA Controller Synthesis from HW /SW Communication Protocol Specifications.	Design Autom. for Emb. Sys.	2001	DBLP DOI BibTeX RDF
1	Andrew Bardsley, Doug A. Edwards	Synthesising an asynchronous DMA controller with Balsa.	Journal of Systems Architecture	2000	DBLP DOI BibTeX RDF
1	Mattias O'Nils, Axel Jantsch	Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
1	Edgar Holmann, Toyohiko Yoshida, Akira Yamada, Shin-ichi Uramoto	Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding.	VLSI Signal Processing	1998	DBLP DOI BibTeX RDF
1	Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li	Protected, User-Level DMA for the SHRIMP Network Interface.	HPCA	1996	DBLP DOI BibTeX RDF	SHRIMP network interface, User-level Direct Memory Access, DMA transfers, permission checking, virtual memory translation, operating system, computer networks, file organisation, network interfaces, DMA, address translation, computer interfaces
1	M. Esen Tuna, Kamlesh Rath, Steven D. Johnson	Specification and synthesis of bounded indirection.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	bounded indirection, complex control structures, dynamic connections, control state indirection, value indirection, net indirection, behavior tables, data path descriptions, DMA controller, formal specification, high level synthesis, finite state machines, interrupts, interrupts, continuations, hardware description languages, hardware description languages, pointers, system specification, data flow computing, control system CAD
1	Myung Hoon Sunwoo, J. K. Aggarwal	A Sliding Memory Plane Array Processor.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	sliding memory, plane array processor, mesh-connected, single-input multiple-data, SliM, image processing, image processing, parallel architectures
1	S. Leventis, George D. Papadopoulos, Stavros A. Koubias, J. Constantinides	A protocol for a new double-loop computer network and its implementation.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF