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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 21 occurrences of 12 keywords
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Results
Found 52 publication records. Showing 52 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Finn Haedicke, Daniel Große, Rolf Drechsler |
A guiding coverage metric for formal verification.  |
DATE  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging reversible circuits. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler |
Simulation-based equivalence checking between SystemC models at different levels of abstraction. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Michael, Daniel Große, Rolf Drechsler |
Analyzing dependability measures at the Electronic System Level. |
FDL |
2011 |
DBLP BibTeX RDF |
|
| 1 | Mohamed Bawadekji, Daniel Große, Rolf Drechsler |
TLM protocol compliance checking at the Electronic System Level. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Towards Fully Automatic Synthesis of Embedded Software. |
Embedded Systems Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
Quality-Driven SystemC Design |
|
2010 |
RDF |
|
| 1 | Daniel Große, Hoang M. Le, Rolf Drechsler |
Proving transaction and system-level properties of untimed SystemC TLM designs. |
MEMOCODE |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang M. Le, Daniel Große, Rolf Drechsler |
Towards analyzing functional coverage in SystemC TLM property checking. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang M. Le, Daniel Große, Rolf Drechsler |
Automatic Fault Localization for SystemC TLM Designs. |
MTV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits. |
Multiple-Valued Logic and Soft Computing |
2009 |
DBLP BibTeX RDF |
|
| 1 | André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
WoLFram- A Word Level Framework for Formal Verification. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler |
Contradictory antecedent debugging in bounded model checking. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
formal verification, debugging, bounded model checking, psl |
| 1 | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
Equivalence Checking of Reversible Circuits. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler |
SMT-based stimuli generation in the SystemC Verification library. |
FDL |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
Reversible Logic Synthesis with Output Permutation. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Property analysis and design understanding. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler |
Debugging of Toffoli networks. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Daniel Große, Hoang M. Le, Rolf Drechsler |
Induction-Based Formal Verification of SystemC TLM Designs. |
MTV |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Analyzing Functional Coverage in Bounded Model Checking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler |
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, Synthesis, Reversible Logic |
| 1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
Synthesis, Boolean Satisfiability, Reversible Logic |
| 1 | Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler |
Contradiction Analysis for Constraint-based Random Simulation. |
FDL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große |
Quantified Synthesis of Reversible Logic. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große |
Quality-Driven Design and Verification Flow for Digital Systems. |
Ausgezeichnete Informatikdissertationen |
2008 |
DBLP BibTeX RDF |
|
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. |
MTV |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulrich Kühne, Daniel Große, Rolf Drechsler |
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
SWORD: A SAT like prover using word level information. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler |
Exact sat-based toffoli network synthesis. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
synthesis, minimization, boolean satisfiability, reversible logic, quantum circuits |
| 1 | Daniel Große, Rüdiger Ebendt, Rolf Drechsler |
Improvements for constraint solving in the systemc verification library. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
constraint-based randomization, systemC verification library, systemC |
| 1 | Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler |
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. |
FDL |
2007 |
DBLP BibTeX RDF |
|
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Estimating functional coverage in bounded model checking. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Daniel Große |
Fast exact Toffoli network synthesis of reversible logic. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW co-verification of embedded systems using bounded model checking. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
hardware/software co-verification, embedded systems, formal verification, SystemC, bounded model checking, PSL |
| 1 | Görschwin Fey, Daniel Große, Rolf Drechsler |
Avoiding false negatives in formal verification for protocol-driven blocks. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große |
SyCE: An Integrated Environment for System Design in SystemC. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
Acceleration of SAT-Based Iterative Property Checking. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
CheckSyC: an efficient property checker for RTL SystemC designs. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. |
GI Jahrestagung |
2005 |
DBLP BibTeX RDF |
|
| 1 | Daniel Große, Ulrich Kühne, Rolf Drechsler |
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. |
MTV |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
Checkers for SystemC designs. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. |
it - Information Technology |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Görschwin Fey, Rolf Drechsler |
Modeling Multi-Valued Circuits in SystemC. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst |
Efficient Automatic Visualization of SystemC Designs. |
FDL |
2003 |
DBLP BibTeX RDF |
|
| 1 | Daniel Große, Rolf Drechsler |
Formal verification of LTL formulas for SystemC designs. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler |
Heuristic Learning Based on Genetic Programming. |
Genetic Programming and Evolvable Machines |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Daniel Große |
Reachability Analysis for Formal Verification of SystemC. |
DSD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler |
Heuristic Learning Based on Genetic Programming. |
EuroGP |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker |
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. |
Fuzzy Days |
2001 |
DBLP DOI BibTeX RDF |
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