Search results for "Daniel J. Sorin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin	Address Translation Aware Memory Consistency.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Mark D. Hill, David A. Wood	A Primer on Memory Consistency and Cache Coherence		2011	DOI RDF
1	Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, A. Biswas, Xavier Vera	Architectures for online error detection and recovery in multicore processors.	DATE	2011	DBLP BibTeX RDF
1	Patrick J. Eibl, Albert Meixner, Daniel J. Sorin	An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2.	SIGMETRICS	2011	DBLP DOI BibTeX RDF
1	Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin	Fractal Consistency: Architecting the Memory System to Facilitate Verification.	Computer Architecture Letters	2010	DBLP DOI BibTeX RDF
1	Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin	Specifying and dynamically verifying address translation-aware memory consistency.	ASPLOS	2010	DBLP DOI BibTeX RDF	virtual memory, memory consistency, address translation, dynamic verification
1	Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin	Fractal Coherence: Scalably Verifiable Cache Coherence.	MICRO	2010	DBLP DOI BibTeX RDF
1	Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy	UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.	HPCA	2010	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Daniel J. Sorin	Fault Tolerant Computer Architecture		2009	DOI RDF
1	Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen	Multicore power management: Ensuring robustness via early-stage formal verification.	MEMOCODE	2009	DBLP DOI BibTeX RDF
1	Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin	Dynamic power gating with quality guarantees.	ISLPED	2009	DBLP DOI BibTeX RDF	execution units, low power, power management, microarchitecture, power gating
1	Meng Zhang, Anita Lungu, Daniel J. Sorin	Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms.	DFT	2009	DBLP DOI BibTeX RDF
1	Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin	Reduced Precision Checking for a Floating Point Adder.	DFT	2009	DBLP DOI BibTeX RDF
1	Fred A. Bower, Daniel J. Sorin, Landon P. Cox	The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling.	IEEE Micro	2008	DBLP DOI BibTeX RDF
1	Albert Meixner, Michael E. Bauer, Daniel J. Sorin	Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.	IEEE Micro	2008	DBLP DOI BibTeX RDF	fault tolerance, dependability, error detection, microarchitecture
1	Bogdan F. Romanescu, Daniel J. Sorin	Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults.	PACT	2008	DBLP DOI BibTeX RDF	lifetime performance, fault tolerance, reliability, multicore
1	Albert Meixner, Daniel J. Sorin	Detouring: Translating software to circumvent hard faults in simple cores.	DSN	2008	DBLP DOI BibTeX RDF
1	Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin	Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	microarchitecture, process variability
1	Fred A. Bower, Daniel J. Sorin, Sule Ozev	Online diagnosis of hard faults in microprocessors.	TACO	2007	DBLP DOI BibTeX RDF	Hard fault tolerance, fine-grained diagnosis, processor microarchitecture
1	Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin	VariaSim: simulating circuits and systems in the presence of process variability.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Jonathan R. Carter, Sule Ozev, Daniel J. Sorin	Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown	CoRR	2007	DBLP BibTeX RDF
1	Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev	Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation.	PACT	2007	DBLP DOI BibTeX RDF
1	Anita Lungu, Daniel J. Sorin	Verification-Aware Microprocessor Design.	PACT	2007	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Error Detection Using Dynamic Dataflow Verification.	PACT	2007	DBLP DOI BibTeX RDF
1	Albert Meixner, Michael E. Bauer, Daniel J. Sorin	Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.	MICRO	2007	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Unified microprocessor core storage.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	unified caching, resource allocation, microarchitecture, power-efficiency
1	Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin	Lazy Error Detection for Microprocessor Functional Units.	DFT	2007	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures.	HPCA	2007	DBLP DOI BibTeX RDF
1	Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.	ICCD	2007	DBLP DOI BibTeX RDF
1	Tong Li, Alvin R. Lebeck, Daniel J. Sorin	Spin Detection Hardware for Improved Management of Multithreaded Systems.	IEEE Trans. Parallel Distrib. Syst.	2006	DBLP DOI BibTeX RDF	multithreaded system, scheduling, synchronization, virtualization, multiprocessor, Deadlock, spinning, performance counter, livelock
1	Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin	NANA: A nano-scale active network architecture.	JETC	2006	DBLP DOI BibTeX RDF	Accumulator ISA, defect isolation, reverse path forwarding, active network, DNA, defect tolerance, self-assembly, carbon nanotube, nanoelectronics, nanocomputing
1	Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin	Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.	ITC	2006	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures.	DSN	2006	DBLP DOI BibTeX RDF
1	Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev	Applying architectural vulnerability Analysis to hard faults in the microprocessor.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	hard-fault tolerance, reliability, computer architecture
1	Fred A. Bower, Sule Ozev, Daniel J. Sorin	Autonomic Microprocessor Execution via Self-Repairing Arrays.	IEEE Trans. Dependable Sec. Comput.	2005	DBLP DOI BibTeX RDF	Logic design reliability and testing, microprocessors and microcomputers
1	Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood	Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin	Self-Assembled Architectures and the Temporal Aspects of Computing.	IEEE Computer	2005	DBLP DOI BibTeX RDF
1	Albert Meixner, Daniel J. Sorin	Dynamic Verification of Sequential Consistency.	ISCA	2005	DBLP DOI BibTeX RDF
1	Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin	Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution.	USENIX Annual Technical Conference, General Track	2005	DBLP BibTeX RDF
1	Fred A. Bower, Daniel J. Sorin, Sule Ozev	A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
1	Jonathan R. Carter, Sule Ozev, Daniel J. Sorin	Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown.	DATE	2005	DBLP DOI BibTeX RDF
1	Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin	Communication breakdown: analyzing CPU usage in commercial Web workloads.	ISPASS	2004	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood	Using Speculation to Simplify Multiprocessor Design.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin	Tolerating Hard Faults in Microprocessor Array Structures.	DSN	2004	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon	Analytic Evaluation of Shared-Memory Architectures.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	performance evaluation, heterogeneity, Analytical model, shared memory multiprocessor, mean value analysis
1	Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin	Simulating a $2M Commercial Server on a $2K PC.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood	Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Mark D. Hill, David A. Wood	Dynamic Verification of End-to-End Multiprocessor Invariants.	DSN	2003	DBLP DOI BibTeX RDF
1	Tong Li, Alvin R. Lebeck, Daniel J. Sorin	Quantifying instruction criticality for shared memory multiprocessors.	SPAA	2003	DBLP DOI BibTeX RDF	shared memory multiprocessors, slack, critical path analysis
1	Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood	Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	multicast snooping, Cache coherence, protocol verification, protocol specification, memory consistency
1	Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood	SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	multiprocessor, availability, shared memory
1	Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood	Bandwidth Adaptive Snooping.	HPCA	2002	DBLP DOI BibTeX RDF	adaptive, shared-memory multiprocessors, coherence protocols, snooping
1	Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti	Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.	MICRO	2001	DBLP DOI BibTeX RDF
1	Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood	Timestamp snooping: an approach for extending SMPs.	ASPLOS	2000	DBLP DOI BibTeX RDF
1	Derek L. Eager, Daniel J. Sorin, Mary K. Vernon	AMVA techniques for high service time variability.	SIGMETRICS	2000	DBLP DOI BibTeX RDF
1	E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood	Multicast Snooping: A New Coherence Method Using a Multicast Address Network.	ISCA	1999	DBLP DOI BibTeX RDF
1	Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin	A System-Level Specification Framework for I/O Architectures.	SPAA	1999	DBLP DOI BibTeX RDF
1	Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin	Using Lamport Clocks to Reason about Relaxed Memory Models.	HPCA	1999	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood	Analytic Evaluation of Shared-memory Systems with ILP Processors.	ISCA	1998	DBLP DOI BibTeX RDF
1	Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill	Lamport Clocks: Verifying a Directory Cache-Coherence Protocol.	SPAA	1998	DBLP DOI BibTeX RDF

Publications of "Daniel J. Sorin" ( http://dblp.L3S.de/Authors/Daniel_J._Sorin )