Search results for "David H. Albonesi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo	A phase adaptive cache hierarchy for SMT processors.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, David H. Albonesi	ReMAP: A Reconfigurable Architecture for Chip Multiprocessors.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Mark J. Cianchetti, David H. Albonesi	A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors.	JETC	2011	DBLP DOI BibTeX RDF
1	David H. Albonesi	Future Directions in Computer Architecture Research.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	David H. Albonesi	Moving Forward.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo	Adaptive Cache Memories for SMT Processors.	DSD	2010	DBLP DOI BibTeX RDF
1	Jonathan A. Winter, David H. Albonesi, Christine A. Shoemaker	Scalable thread scheduling and global power management for heterogeneous many-core architectures.	PACT	2010	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, David H. Albonesi	Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors.	PACT	2010	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, David H. Albonesi	ReMAP: A Reconfigurable Heterogeneous Multicore Architecture.	MICRO	2010	DBLP DOI BibTeX RDF
1	David H. Albonesi	From the Editor in Chief: Welcome A-Board.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi	Phastlane: a rapid transit optical routing network.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, multicore, optical interconnects, nanophotonics
1	David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez (eds.)	42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA	MICRO	2009	DBLP BibTeX RDF
1	Jonathan A. Winter, David H. Albonesi	Addressing thermal nonuniformity in SMT workloads.	TACO	2008	DBLP DOI BibTeX RDF	adaptive microarchitectures, dynamic voltage scaling, Simultaneous multithreading, dynamic thermal management, clustered microarchitectures
1	David H. Albonesi	Changes Ahead.	IEEE Micro	2008	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi	Shared reconfigurable architectures for CMPS.	FPL	2008	DBLP DOI BibTeX RDF
1	Jonathan A. Winter, David H. Albonesi	Scheduling algorithms for unpredictably heterogeneous CMP architectures.	DSN	2008	DBLP DOI BibTeX RDF
1	David H. Albonesi	Editor in Chief's Message: Truly "hot" chips - Do we still care?	IEEE Micro	2007	DBLP DOI BibTeX RDF	high-performance microprocessors, power management, power-aware architectures, multicore chips
1	David H. Albonesi	Mixing It Up.	IEEE Micro	2007	DBLP DOI BibTeX RDF	photonic integration, self-reconfigurable hardware, simulation
1	David H. Albonesi	More Hot Stuff.	IEEE Micro	2007	DBLP DOI BibTeX RDF	power management, environment, ecology, power-aware architectures, multicore chips
1	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	On-Chip Optical Technology in Future Bus-Based Multicore Designs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	optical technology, snoopy bus, chip multiprocessor, on-chip interconnect
1	David H. Albonesi	Productive and Healthy Debate.	IEEE Micro	2007	DBLP DOI BibTeX RDF	single-threaded, security, reliability, low power, computer architecture, multithreaded, debates
1	David H. Albonesi	Standing on Solid Ground.	IEEE Micro	2007	DBLP DOI BibTeX RDF	interconnects for multicore chips, special-purpose chips, debugging, human-computer interface, microarchitecture, programmability
1	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman	Predictions of CMOS compatible on-chip optical interconnect.	Integration	2007	DBLP DOI BibTeX RDF
1	Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares	Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors.	PACT	2007	DBLP DOI BibTeX RDF
1	Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares	Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.	HiPEAC	2007	DBLP DOI BibTeX RDF
1	YongKang Zhu, David H. Albonesi	Synergistic temperature and energy management in GALS processor architectures.	ISLPED	2006	DBLP DOI BibTeX RDF	dynamic temperature management (DTM), dynamic voltage scaling (DVS)
1	Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya Dwarkadas	Compatible phase co-scheduling on a CMP of multi-threaded processors.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi	Leveraging Optical Technology in Future Bus-based Chip Multiprocessors.	MICRO	2006	DBLP DOI BibTeX RDF
1	YongKang Zhu, David H. Albonesi	Localized microarchitecture-level voltage management.	ISCAS	2006	DBLP DOI BibTeX RDF
1	M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi	Power-Efficient Error Tolerance in Chip Multiprocessors.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Fault-tolerance, low-power design
1	Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas	Partitioning Multi-Threaded Processors with a Large Number of Threads.	ISPASS	2005	DBLP DOI BibTeX RDF
1	YongKang Zhu, David H. Albonesi, Alper Buyuktosunoglu	A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.	ISPASS	2005	DBLP DOI BibTeX RDF
1	M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi	Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Predictions of CMOS compatible on-chip optical interconnect.	SLIP	2005	DBLP DOI BibTeX RDF	CMOS compatible, on-chip, optical interconnect, trends
1	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Electrical and optical on-chip interconnects in scaled microprocessors.	ISCAS	2005	DBLP DOI BibTeX RDF
1	David H. Albonesi	Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina	An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications.	Journal of Circuits, Systems, and Computers	2004	DBLP DOI BibTeX RDF
1	YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi	The Energy Impact of Aggressive Loop Fusion.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott	Dynamically Trading Frequency for Complexity in a GALS Microprocessor.	MICRO	2004	DBLP DOI BibTeX RDF
1	Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott	Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Pradip Bose, David H. Albonesi, Diana Marculescu	Guest Editors' Introduction: Power and Complexity Aware Design.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
1	David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster	Dynamically Tuning Processor Resources with Adaptive Processing.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho	Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Ali El-Moursy, David H. Albonesi	Front-End Policies for Improved Issue Efficiency in SMT Processors.	HPCA	2003	DBLP DOI BibTeX RDF
1	Lei Chen, Steve Dropsho, David H. Albonesi	Dynamic Data Dependence Tracking and its Application to Branch Prediction.	HPCA	2003	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster	Tradeoffs in power-efficient issue queue design.	ISLPED	2002	DBLP DOI BibTeX RDF	non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue
1	Wael El-Essawy, David H. Albonesi, Balaram Sinharoy	A microarchitectural-level step-power analysis tool.	ISLPED	2002	DBLP DOI BibTeX RDF	Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise
1	Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott	Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott	Dynamic frequency and voltage control for a multiple clock domain microarchitecture.	MICRO	2002	DBLP DOI BibTeX RDF
1	Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman	Managing static leakage energy in microprocessor functional units.	MICRO	2002	DBLP DOI BibTeX RDF
1	Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas	Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.	PACS	2002	DBLP DOI BibTeX RDF
1	Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott	Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.	HPCA	2002	DBLP DOI BibTeX RDF	Off-Line Analysis Tool, Dynamic Reconfiguration Algorithm, Low Power, Dynamic Voltage and Frequency Scaling, Multiple Clock Domain
1	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically allocating processor resources between nearby and distant ILP.	ISCA	2001	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook	A circuit level implementation of an adaptive issue queue for power-aware microprocessors.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
1	Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi	Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors.	VLSI-SOC	2001	DBLP BibTeX RDF
1	David H. Albonesi	Selective Cache Ways: On-Demand Cache Resource Allocation.	J. Instruction-Level Parallelism	2000	DBLP BibTeX RDF
1	Bingxiong Xu, David H. Albonesi	Runtime Reconfiguration Techniques for Efficient General-Purpose Computation.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.	MICRO	2000	DBLP DOI BibTeX RDF
1	Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi	An Adaptive Issue Queue for Reduced Power at High Performance.	PACS	2000	DBLP DOI BibTeX RDF
1	David H. Albonesi, Israel Koren	STATS: A framework for microprocessor and system-level design space exploration.	Journal of Systems Architecture	1999	DBLP DOI BibTeX RDF
1	David H. Albonesi	Selective Cache Ways: On-Demand Cache Resource Allocation. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	David H. Albonesi	An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures.	VLSI	1999	DBLP BibTeX RDF
1	David H. Albonesi	Dynamic IPC/Clock Rate Optimization.	ISCA	1998	DBLP DOI BibTeX RDF
1	David H. Albonesi, Israel Koren	Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems.	IEEE PACT	1997	DBLP DOI BibTeX RDF
1	David H. Albonesi, Israel Koren	A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques.	International Journal of Parallel Programming	1996	DBLP BibTeX RDF
1	David H. Albonesi, Israel Koren	Tradeoffs in the Design of Single Chip Multiprocessors.	IFIP PACT	1994	DBLP BibTeX RDF

Publications of "David H. Albonesi" ( http://dblp.L3S.de/Authors/David_H._Albonesi )