Search results for "Davide Bertozzi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini	Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.	DATE	2012	DBLP BibTeX RDF
1	Alessandro Strano, Carles Hernández, Federico Silla, Davide Bertozzi	Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.	IJERTCS	2011	DBLP DOI BibTeX RDF
1	Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato	Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Giacomo Paci, Davide Bertozzi, Luca Benini	Variability compensation for full-swing against low-swing on-chip communication.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi	System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Alessandro Strano, Davide Bertozzi, Arnaud Grasset, Sami Yehia	Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration.	ASAP	2011	DBLP DOI BibTeX RDF
1	Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi	Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.	DATE	2011	DBLP BibTeX RDF
1	Alessandro Strano, Daniele Ludovici, Davide Bertozzi	A library of dual-clock FIFOs for cost-effective and flexible MPSoC design.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Francisco Gilabert Villamón, María Engracia Gómez, Simone Medardoni, Davide Bertozzi	Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip.	NOCS	2010	DBLP DOI BibTeX RDF
1	Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato	Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.	NOCS	2010	DBLP DOI BibTeX RDF	Fault-tolerance, Routing, Networks-on-chip
1	Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi	Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.	DATE	2010	DBLP BibTeX RDF
1	Martino Ruggiero, Davide Bertozzi, Luca Benini, Michela Milano, A. Andrei	Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Kees Goossens	Networks on chips [editorial].	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato	Efficient implementation of distributed routing algorithms for NoCs.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini, Georgi Gaydadjiev	Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.	NOCS	2009	DBLP DOI BibTeX RDF
1	Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini	Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	link design techniques, network-on-chip
1	Francisco Gilabert Villamón, Daniele Ludovici, Simone Medardoni, Davide Bertozzi, Luca Benini, Georgi Nedeltchev Gaydadjiev	Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.	CISIS	2009	DBLP DOI BibTeX RDF
1	Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi	Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.	DATE	2009	DBLP BibTeX RDF
1	Giacomo Paci, Davide Bertozzi, Luca Benini	Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.	DATE	2009	DBLP BibTeX RDF
1	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Michela Milano, Luca Benini	A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	scheduling, Integer Programming, Constraint Programming, MPSoCs, allocation
1	Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev	A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hardware space exploration, embedded system design, Multiprocessor system-on-chip, real time analysis, electrocardiogram algorithms
1	Francisco Gilabert Villamón, Simone Medardoni, Davide Bertozzi, Luca Benini, María Engracia Gómez, Pedro López, José Duato	Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.	NOCS	2008	DBLP DOI BibTeX RDF	Interconnection networks, networks on chip, topologies, chip design
1	Alberto Ferrante, Simone Medardoni, Davide Bertozzi	Network Interface Sharing Techniques for Area Optimized NoC Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Luca Benini, Davide Bertozzi, Michela Milano	Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming.	ICLP	2008	DBLP DOI BibTeX RDF
1	Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii	Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.	DATE	2008	DBLP DOI BibTeX RDF
1	Simone Medardoni, Marcello Lajolo, Davide Bertozzi	Variation tolerant NoC design by means of self-calibrating links.	DATE	2008	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Shashi Kumar, Maurizio Palesi	Networks-on-Chip: Emerging Research Topics and Novel Ideas.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson	Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	HW/SW, hardware space exploration, embedded system design, Multiprocessor System-on-Chip, real-time analysis, electrocardiogram algorithms
1	Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino	Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	embedded multimedia, low power, energy efficiency, MPSoCs, programming models, task-level parallelism
1	Simone Medardoni, Davide Bertozzi, Enrico Macii	Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	RTL synthesis, leakage-aware, power management, selection strategy
1	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
1	Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini	Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	realtime analysis, design space exploration, multiprocessor system-on-chip, biomedical, electrocardiogram algorithms
1	Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev	A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	hardware space exploration, embedded system design, multiprocessor system-on-chip, real-time analysis, electrocardiogram algorithms
1	Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson	MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	hardware space exploration, multiprocessor system-on-chip, real-time analysis, electrocardiogram algorithms
1	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano	Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip.	DATE	2006	DBLP DOI BibTeX RDF
1	Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali	Supporting task migration in multi-processor systems-on-chip: a feasibility study.	DATE	2006	DBLP DOI BibTeX RDF
1	Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano	Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs.	CPAIOR	2006	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli	NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	architecture, Systems-on-chip, mapping, networks on chip, synthesis
1	Davide Bertozzi, Luca Benini, Giovanni De Micheli	Error control schemes for on-chip communication links: the energy-reliability tradeoff.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri	MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	system-on-chip simulation, design space exploration, multiprocessor embedded systems
1	Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano, Francesco Poletti	Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip.	Intelligenza Artificiale	2005	DBLP BibTeX RDF
1	Davide Bertozzi, Luca Benini, Giovanni De Micheli	Network On-Chip Design for Gigascale Systems-on-Chip.	The Industrial Information Technology Handbook	2005	DBLP BibTeX RDF
1	Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano	Allocation and Scheduling for MPSoCs via decomposition and no-good generation.	IJCAI	2005	DBLP BibTeX RDF
1	Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini	Fault tolerance overhead in network-on-chip flow control schemes.	SBCCI	2005	DBLP DOI BibTeX RDF	fault tolerance, network on chip, error correction, flow control
1	Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli	ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips.	DATE	2005	DBLP DOI BibTeX RDF
1	Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano	Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation.	CP	2005	DBLP DOI BibTeX RDF
1	Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini	Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms.	ICCD	2005	DBLP DOI BibTeX RDF
1	Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon	Analyzing On-Chip Communication in a MPSoC Environment.	DATE	2004	DBLP DOI BibTeX RDF
1	Francesco Poletti, Davide Bertozzi, Luca Benini, Alessandro Bogliolo	Performance Analysis of Arbitration Policies for SoC Communication Architectures.	Design Autom. for Emb. Sys.	2003	DBLP DOI BibTeX RDF
1	Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino	SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi	Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.	DATE	2003	DBLP DOI BibTeX RDF
1	Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini	xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs.	ICCD	2003	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Luca Benini, Bruno Riccò	Parametric timing and power macromodels for high level simulation of low-swing interconnects.	ISLPED	2002	DBLP DOI BibTeX RDF	delay, interconnect, power, macromodel, low-swing
1	Davide Bertozzi, Luca Benini, Giovanni De Micheli	Low Power Error Resilient Encoding for On-Chip Data Buses.	DATE	2002	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Luca Benini, Bruno Riccò	Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino	Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.	ICCD	2002	DBLP DOI BibTeX RDF

Publications of "Davide Bertozzi" ( http://dblp.L3S.de/Authors/Davide_Bertozzi )