Search results for "Dean M. Tullsen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Houman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, Dean M. Tullsen	Hot peripheral thermal management to mitigate cache temperature variation.	ISQED	2012	DBLP DOI BibTeX RDF
1	Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen	Execution migration in a heterogeneous-ISA chip multiprocessor.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Houman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, Dean M. Tullsen	Dynamically heterogeneous cores through 3D resource pooling.	HPCA	2012	DBLP DOI BibTeX RDF
1	Subhradyuti Sarkar, Dean M. Tullsen	Data Layout for Cache Performance on a Multithreaded Architecture.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Md Kamruzzaman, Steven Swanson, Dean M. Tullsen	Inter-core prefetching for multicore processors using migrating helper threads.	ASPLOS	2011	DBLP DOI BibTeX RDF
1	Hung-Wei Tseng, Dean M. Tullsen	Data-triggered threads: Eliminating redundant computation.	HPCA	2011	DBLP DOI BibTeX RDF
1	Jeffery A. Brown, Leo Porter, Dean M. Tullsen	Fast thread migration via cache working set prediction.	HPCA	2011	DBLP DOI BibTeX RDF
1	Matthew DeVuyst, Dean M. Tullsen, Seon Wook Kim	Runtime parallelization of legacy code on a transactional memory system.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Md Kamruzzaman, Steven Swanson, Dean M. Tullsen	Software data spreading: leveraging distributed caches to improve single thread performance.	PLDI	2010	DBLP DOI BibTeX RDF	single-thread performance, compilers, chip multiprocessors
1	Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew	Dynamic workload characterization for power efficient scheduling on CMP systems.	ISLPED	2010	DBLP DOI BibTeX RDF	power, multi-cores, workload characterization
1	Subhra Mazumdar, Dean M. Tullsen, Justin J. Song	Inter-socket victim cacheing for platform power reduction.	ICCD	2010	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen	Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08).	SIGARCH Computer Architecture News	2009	DBLP DOI BibTeX RDF
1	Joel S. Emer, Dean M. Tullsen	Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Richard D. Strong, Jayaram Mudigonda, Jeffrey C. Mogul, Nathan L. Binkert, Dean M. Tullsen	Fast switching of threads between cores.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Leo Porter, Bumyong Choi, Dean M. Tullsen	Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading.	PACT	2009	DBLP DOI BibTeX RDF
1	Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
1	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
1	Leo Porter, Dean M. Tullsen	Creating artificial global history to improve branch prediction accuracy.	ICS	2009	DBLP DOI BibTeX RDF	branch prediction
1	Ayse Kivilcim Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing	Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	reliability, chip multiprocessors, thermal management, simulation methodology
1	Brad Calder, Dean M. Tullsen	Editorial.	TACO	2008	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen	Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07).	SIGARCH Computer Architecture News	2008	DBLP DOI BibTeX RDF
1	Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF	Speculative thread level parallelism, pre-computation slices, thread partitioning, multi-core architecture
1	Bumyong Choi, Leo Porter, Dean M. Tullsen	Accurate branch prediction for short threads.	ASPLOS	2008	DBLP DOI BibTeX RDF	chip multiprocessors, branch prediction
1	Jeffery A. Brown, Dean M. Tullsen	The shared-thread multiprocessor.	ICS	2008	DBLP DOI BibTeX RDF	chip multiprocessors, simultaneous multithreading
1	Dean M. Tullsen	Holistic Design of Multiple-Core Architectures.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Subhradyuti Sarkar, Dean M. Tullsen	Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Brad Calder, Dean M. Tullsen	Introduction.	TACO	2007	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi	Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06).	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Ravi Iyer, Dean M. Tullsen	Editorial: Special Section on CMP Architectures.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen	The architecture of Efficient Multi-Core Processors: A Holistic Approach.	Advances in Computers	2007	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Brad Calder (eds.)	34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA	ISCA	2007	DBLP BibTeX RDF
1	Dean M. Tullsen	HCW Keynote Address Holistic Design of Multi-Core Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen	Proximity-aware directory-based coherence for multi-core processor architectures.	SPAA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, coherence
1	Weifeng Zhang, Dean M. Tullsen, Brad Calder	Accelerating and Adapting Precomputation Threads for Effcient Prefetching.	HPCA	2007	DBLP DOI BibTeX RDF
1	Brad Calder, Dean M. Tullsen	Introduction.	TACO	2006	DBLP DOI BibTeX RDF
1	Weifeng Zhang, Brad Calder, Dean M. Tullsen	A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework.	CGO	2006	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi	Core architecture optimization for heterogeneous chip multiprocessors.	PACT	2006	DBLP DOI BibTeX RDF	computer architecture, multi-core architectures, heterogeneous chip multiprocessors
1	M. De Vuyst, Rakesh Kumar, Dean M. Tullsen	Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors.	IPDPS	2006	DBLP DOI BibTeX RDF
1	David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
1	David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Weifeng Zhang, Brad Calder, Dean M. Tullsen, Steve Checkoway	Speculative Code Value Specialization Using the Trace Cache Fill Unit.	ICCD	2006	DBLP BibTeX RDF
1	Brad Calder, Dean M. Tullsen	Introduction.	TACO	2005	DBLP DOI BibTeX RDF
1	Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou	The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best.	Computer Architecture Letters	2005	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen	Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan	Heterogeneous Chip Multiprocessors.	IEEE Computer	2005	DBLP DOI BibTeX RDF	Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing
1	Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen	Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices.	PLDI	2005	DBLP DOI BibTeX RDF	pre-computation slices, automatic parallelization, thread-level parallelism, speculative multithreading
1	Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh	A Tree Based Router Search Engine Architecture with Single Port Memories.	ISCA	2005	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.	ISCA	2005	DBLP DOI BibTeX RDF
1	Weifeng Zhang, Brad Calder, Dean M. Tullsen	An Event-Driven Multithreaded Dynamic Optimization Framework.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Nathan Tuck, Dean M. Tullsen	Multithreaded Value Prediction.	HPCA	2005	DBLP DOI BibTeX RDF
1	Brad Calder, Dean M. Tullsen	Introduction.	TACO	2004	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas	Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.	ISCA	2004	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen	Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder	Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy.	MICRO	2004	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003	Control Flow Optimization Via Dynamic Reconvergence Prediction.	MICRO	2004	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.	Computer Architecture Letters	2003	DBLP DOI BibTeX RDF	chip multiprocessor, low-power architecture
1	John S. Seng, Dean M. Tullsen	The Effect of Compiler Optimizations on Pentium 4 Power Consumption.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
1	Nathan Tuck, Dean M. Tullsen	Initial Observations of the Simultaneous Multithreading Pentium 4 Processor.	IEEE PACT	2003	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.	MICRO	2003	DBLP DOI BibTeX RDF
1	John S. Seng, Dean M. Tullsen	Exploring the Potential of Architecture-Level Power Optimizations.	PACS	2003	DBLP DOI BibTeX RDF
1	Eric Tune, Dean M. Tullsen, Brad Calder	Quantifying Instruction Criticality.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Dean M. Tullsen	Compiling for instruction cache performance on a multithreaded architecture.	MICRO	2002	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen	Pointer cache assisted prefetching.	MICRO	2002	DBLP DOI BibTeX RDF
1	Allan Snavely, Dean M. Tullsen, Geoffrey M. Voelker	Symbiotic jobscheduling with priorities for a simultaneous multithreading processor.	SIGMETRICS	2002	DBLP DOI BibTeX RDF	job scheduling, priorities, simultaneous multithreading
1	Jamison D. Collins, Dean M. Tullsen	Runtime identification of cache conflict misses: The adaptive miss buffer.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	adaptive miss buffer, cache exclusion, prefetching, victim cache, Cache architecture, conflict misses
1	Jamison D. Collins, Hong Wang 0003, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen	Speculative precomputation: long-range prefetching of delinquent loads.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
1	John S. Seng, Eric Tune, Dean M. Tullsen	Reducing power with dynamic critical path information.	MICRO	2001	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Dynamic speculative precomputation.	MICRO	2001	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Jeffery A. Brown	Handling long-latency loads in a simultaneous multithreading processor.	MICRO	2001	DBLP DOI BibTeX RDF
1	Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder	Dynamic Prediction of Critical Path Instructions.	HPCA	2001	DBLP DOI BibTeX RDF
1	Barbara Kreaseck, Dean M. Tullsen, Brad Calder	Limits of task-based parallelism in irregular applications.	SIGARCH Computer Architecture News	2000	DBLP DOI BibTeX RDF
1	Allan Snavely, Dean M. Tullsen	Symbiotic Jobscheduling for a Simultaneous Multithreading Processor.	ASPLOS	2000	DBLP DOI BibTeX RDF
1	Barbara Kreaseck, Dean M. Tullsen, Brad Calder	Limits of Task-Based Parallelism in Irregular Applications.	ISHPC	2000	DBLP DOI BibTeX RDF
1	John S. Seng, Dean M. Tullsen, George Cai	Power-Sensitive Multithreaded Architecture. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	International Journal of Parallel Programming	1999	DBLP DOI BibTeX RDF
1	Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen	Software-Directed Register Deallocation for Simultaneous Multithreaded Processors.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	architecture, register file, simultaneous multithreading, Multithreaded architecture
1	Dean M. Tullsen, John S. Seng	Storageless Value Prediction Using Prior Register Values.	ISCA	1999	DBLP DOI BibTeX RDF
1	Brad Calder, Glenn Reinman, Dean M. Tullsen	Selective Value Prediction.	ISCA	1999	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen	Hardware Identification of Cache Conflict Misses. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin	Classifying load and store instructions for memory renaming.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF
1	Steven Wallace, Dean M. Tullsen, Brad Calder	Instruction Recycling on a Multiple-Path Processor.	HPCA	1999	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy	Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor.	HPCA	1999	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Guang R. Gao	Multithreaded Execution Architecture and Compilation.	HPCA	1999	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Susan J. Eggers, Henry M. Levy	Simultaneous Multithreading: Maximizing On-Chip Parallelism.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Susan J. Eggers, Henry M. Levy	Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Steven Wallace, Brad Calder, Dean M. Tullsen	Threaded Multiple Path Execution.	ISCA	1998	DBLP DOI BibTeX RDF
1	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
1	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	MICRO	1997	DBLP BibTeX RDF	cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size
1	Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm	Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.	ISCA	1996	DBLP DOI BibTeX RDF
1	Dean M. Tullsen	Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor.	Int. CMG Conference	1996	DBLP BibTeX RDF
1	Dean M. Tullsen, Susan J. Eggers	Effective Cache Prefetching on Bus-Based Multiprocessors	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	bus-based multiprocessors, memory latency hiding, false sharing, cache prefetching
1	Dean M. Tullsen, Susan J. Eggers, Henry M. Levy	Simultaneous Multithreading: Maximizing On-Chip Parallelism.	ISCA	1995	DBLP DOI BibTeX RDF
1	Dean M. Tullsen, Susan J. Eggers	Limitations of Cache Prefetching on a Bus-Based Multiprocessor.	ISCA	1993	DBLP DOI BibTeX RDF

Publications of "Dean M. Tullsen" ( http://dblp.L3S.de/Authors/Dean_M._Tullsen )