Search results for "Delay fault testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Bipul C. Paul, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	adaptive body bias design, statistical analysis, process variation, delay fault testing
3	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
2	Kazuteru Namba, Hideo Ito	Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Two-rail logic circuit, overtesting, testability, monotone function, path delay fault testing
2	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi	SoC Symbolic Simulation: a case study on delay fault testing.	DDECS	2008	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
2	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Controllability of Static CMOS Circuits for Timing Characterization.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Design for test, Delay fault testing, Scan design
2	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod	Dynamic Voltage Scaling Aware Delay Fault Testing.	European Test Symposium	2006	DBLP DOI BibTeX RDF
2	Bipul Chandra Paul, Cassondra Neau, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.	ITC	2004	DBLP DOI BibTeX RDF
2	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.	ITC	2004	DBLP DOI BibTeX RDF
2	Ho Fai Ko, Nicola Nicolici	Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	High-level DFT, Delay-fault testing
2	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
2	Spyros Tragoudas, N. Denny	Path delay fault testing using test points.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	path delay fault simulation (coverage), testing digital circuits, design for testability, Automatic test pattern generation, delay testing, path delay fault testing
2	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
2	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Software-Based Delay Fault Testing of Processor Cores.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
2	Qiang Xu, Nicola Nicolici	Delay Fault Testing of Core-Based Systems-on-a-Chi.	DATE	2003	DBLP DOI BibTeX RDF
2	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi	A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.	ITC	2002	DBLP DOI BibTeX RDF
2	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	IOLTW	2002	DBLP DOI BibTeX RDF
2	Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva	On Applying Incremental Satisfiability to Delay Fault Testing.	DATE	2000	DBLP DOI BibTeX RDF
2	Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy	Enhanced untestable path analysis using edge graphs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
2	Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
2	Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis	On Path Delay Fault Testing of Multiplexer - Based Shifters.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos	Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks.	EDCC	1999	DBLP DOI BibTeX RDF
2	Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas	Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.	DATE	1999	DBLP DOI BibTeX RDF
2	Y. Tsiatouhas, Th. Haniotakis	A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	Built-In Self Test, Delay Fault Testing
2	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial-scan delay fault testing of asynchronous circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken	An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.	VTS	1997	DBLP DOI BibTeX RDF	semiconductor testing, stuck-fault testing, ASIC device, application specific integrated circuits, functional testing, IDDQ testing, delay-fault testing, scan testing
2	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
2	Dimitrios Kagaris, Spyros Tragoudas	Maximum independent sets on transitive graphs and their applications in testing and CAD.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI contexts, physical design automation, scheduling, VLSI, high level synthesis, polynomial time algorithm, CAD tool, channel routing, maximum weighted independent set, path delay fault testing, transitive graphs
2	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An efficient built-in self test method for robust path delay fault testing.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	two-pattern test generator, single-input change pattern testing, robust path delay faults, built-in self test
2	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
2	S. Crepaux-Motte, Mireille Jacomino, Rene David	An algebraic method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method
2	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
2	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
2	Meng-Lieh Sheu, Chung-Len Lee	A programmable multiple-sequence generator for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	programmable multiple-sequence generator, BIST applications, two-dimension-like feedback shift register, deterministic sequence, pseudo-random vectors, sequence segmentation method, stuck-open fault testing, logic testing, delays, built-in self test, sequential circuits, shift registers, delay fault testing, binary sequences, sequential circuit testing, regular structure, MCM testing
2	Weiwei Mao, Michael D. Ciletti	A Simplified Six-waveform Type Method for Delay Fault Testing.	DAC	1989	DBLP DOI BibTeX RDF
1	Zhen Chen, Krishnendu Chakrabarty, Dong Xiang	MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Santino Mele, Michele Favalli	A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	European Test Symposium	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
1	Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	At-speed delay fault testing, Power-aware Testing, Functional power
1	Kazuteru Namba, Takashi Ikeda, Hideo Ito	Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Chiba Scan Delay Fault Testing with Short Test Application Time.	J. Electronic Testing	2010	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Experiments with ABIST test methodology applied to path delay fault testing.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Path-Delay Fault Testing in Embedded Content Addressable Memories.	DSD	2010	DBLP DOI BibTeX RDF
1	Mohammad Tehranipoor, Kenneth M. Butler	Power Supply Noise: A Survey on Effects and Research.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	power supply noise (PSN), transition delay fault testing, timing analysis, design and test, path delay testing
1	Kazuteru Namba, Hideo Ito	Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.	IEICE Transactions	2009	DBLP BibTeX RDF
1	M. Reza Javaheri, Reza Sedaghat	Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies.	Microelectronics Reliability	2009	DBLP DOI BibTeX RDF
1	K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh	Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Jaeyong Chung, Jacob A. Abraham	Recursive Path Selection for Delay Fault Testing.	VTS	2009	DBLP DOI BibTeX RDF
1	Shuangyu Ruan, Kazuteru Namba, Hideo Ito	Soft Error Hardened FF Capable of Detecting Wide Error Pulse.	DFT	2008	DBLP DOI BibTeX RDF
1	Jeremy Lee, Mohammad Tehranipoor	LS-TDF: Low-Switching Transition Delay Fault Pattern Generation.	VTS	2008	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
1	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
1	Bin Li, Lei Fang, Michael S. Hsiao	Efficient power droop aware delay fault testing.	ITC	2007	DBLP DOI BibTeX RDF
1	Takashi Ikeda, Kazuteru Namba, Hideo Ito	Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.	DFT	2007	DBLP DOI BibTeX RDF
1	Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka	Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.	DDECS	2007	DBLP BibTeX RDF
1	Michele Favalli, Cecilia Metra	Interactive presentation: Pulse propagation for the detection of small delay defects.	DATE	2007	DBLP DOI BibTeX RDF
1	Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam	Novel Approach to Clock Fault Testing for High Performance Microprocessors.	VTS	2007	DBLP DOI BibTeX RDF
1	Saravanan Padmanaban, Spyros Tragoudas	Implicit grading of multiple path delay faults.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Fault simulation, decision diagrams, delay fault testing
1	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Yiorgos Makris	Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.	DFT	2006	DBLP DOI BibTeX RDF
1	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers	Deterministic Logic BIST for Transition Fault Testing.	European Test Symposium	2006	DBLP DOI BibTeX RDF	Deterministic logic BIST, delay test
1	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
1	Joonhwan Yi, John P. Hayes	High-level delay test generation for modular circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Delay Fault Testing of Processor Cores in Functional Mode.	IEICE Transactions	2005	DBLP BibTeX RDF
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	look-up table (LUT), FPGA, test, delay fault
1	Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press	Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.	VTS	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak	The Other Side of the Timing Equation: a Result of Clock Faults.	DFT	2005	DBLP DOI BibTeX RDF
1	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-based delay fault self-testing of pipelined processor cores.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz	On Reducing Peak Current and Power during Test.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Spyros Tragoudas, Vijay Nagarandal	On-chip embedding mechanisms for large sets of vectors for delay test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng	Critical path selection for delay fault testing based upon a statistical timing model.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi	DFT for Delay Fault Testing of High-Performance Digital Circuits.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger	On Hazard-free Patterns for Fine-delay Fault Testing.	ITC	2004	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham	On-chip delay measurement for silicon debug.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	design for testability, delay fault testing, silicon debug
1	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	A yield improvement methodology using pre- and post-silicon statistical clock scheduling.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF
1	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Delay Fault Self-Testing of Processor Cores.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Erik Chmelar	FPGA Interconnect Delay Fault Testing.	ITC	2003	DBLP DOI BibTeX RDF
1	Muhammad Nummer, Manoj Sachdev	Testing high-performance pipelined circuits with slow-speed testers.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	high-performance testing, Delay-fault testing, design for delay testability
1	Muhammad Nummer, Manoj Sachdev	DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers.	DATE	2003	DBLP DOI BibTeX RDF	high-performance testing, design for testability, Delay-fault testing, design for delay testability
1	Muhammad Nummer, Manoj Sachdev	A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, delay-fault testing, design for delay testability
1	Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka	On Estimation of Fault Efficiency for Path Delay Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Bram Kruseman, Stefan van den Oetelaar	Detection of Resistive Shorts in Deep Sub-micron Technologies.	ITC	2003	DBLP DOI BibTeX RDF
1	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams	Enhancing test efficiency for delay fault testing using multiple-clocked schemes.	DAC	2002	DBLP DOI BibTeX RDF	transition fault model, delay testing, statistical timing analysis
1	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng	On theoretical and practical considerations of path selection for delay fault testing.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
1	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak	Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.	ITC	2002	DBLP DOI BibTeX RDF
1	Ramesh C. Tekumalla, Scott Davidson	On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.	ITC	2002	DBLP DOI BibTeX RDF
1	Hyungwon Kim, John P. Hayes	Delay fault testing of IP-based designs via symbolic path modeling.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	non-robust test, BIST, random testing, delay testing, robust test
1	Andrzej Krasniewski	Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Muhammad Nummer, Manoj Sachdev	A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.	VTS	2001	DBLP DOI BibTeX RDF	high-performance testing, controlled-delay flip-flop, built-in self test, Delay-fault testing, design for delay testability
1	Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev	Design for Delay Testability in High-Speed Digital ICs.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	BIST, delay-fault testing, design for delay testability, high-speed testing