Search results for "Delay minimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	S. Mostafa Mostafavi, Ehsan Hamadani, Rahim Tafazolli	Delay minimization in multipath routing.	IWCMC	2010	DBLP DOI BibTeX RDF	routing, traffic control, delay minimization
2	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
2	Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu	Exploiting on-chip data behavior for delay minimization.	SLIP	2007	DBLP DOI BibTeX RDF	coding, crosstalk, deep-submicron
2	Brian Carrig, David Denieffe, John Murphy	A relative delay minimization scheme for multiplayer gaming in differentiated services networks.	NETGAMES	2006	DBLP DOI BibTeX RDF	relative delay, QoS, diffserv, network games
2	Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang	Multilevel circuit clustering for delay minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering for delay minimization under a more general delay model.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis	Multi-objective circuit partitioning for cutsize and path-based delay minimization.	ICCAD	2002	DBLP DOI BibTeX RDF
2	Jovanka Ciric, Gin Yee, Carl Sechen	Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic.	DATE	2000	DBLP DOI BibTeX RDF
2	Youxin Gao, D. F. Wong	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.	DATE	2000	DBLP DOI BibTeX RDF
2	Chris C. N. Chu, D. F. Wong	A new approach to simultaneous buffer insertion and wire sizing.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
2	Patrick Vuillod, Luca Benini, Giovanni De Micheli	Generalized matching from theory to application.	ICCAD	1997	DBLP DOI BibTeX RDF	MCNC 91 benchmark suite, algorithmic optimization, generalized matching, library cells, multi-output network, post-mapping optimization, unconstrained delay minimization, logic CAD, power minimization, delay constraints, area minimization, Boolean relation
2	Rajmohan Rajaraman, Martin D. F. Wong	Optimum clustering for delay minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Jason Cong, Yuzheng Ding	On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.	FPGA	1995	DBLP DOI BibTeX RDF
2	Shashidhar Thakur, D. F. Wong	Simultaneous area and delay minimum K-LUT mapping for K-exact networks. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
1	Erin M. Ferguson, Jennifer C. Duthie, S. Travis Waller	Comparing Delay Minimization and Emissions Minimization in the Network Design Problem.	Comp.-Aided Civil and Infrastruct. Engineering	2012	DBLP DOI BibTeX RDF
1	Sameh Sorour, Shahrokh Valaee	Completion Delay Minimization for Instantly Decodable Network Codes	CoRR	2012	DBLP BibTeX RDF
1	Chen Liao, Shiyan Hu	Approximation scheme for restricted discrete gate sizing targeting delay minimization.	J. Comb. Optim.	2011	DBLP DOI BibTeX RDF
1	Yifang Liu, Rupesh S. Shelar, Jiang Hu	Simultaneous Technology Mapping and Placement for Delay Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jing Yang, Sennur Ulukus	Trading Rate for Balanced Queue Lengths for Network Delay Minimization.	IEEE Journal on Selected Areas in Communications	2011	DBLP DOI BibTeX RDF
1	Sameh Sorour, Shahrokh Valaee	Completion Delay Minimization for Instantly Decodable Network Coding with Limited Feedback.	ICC	2011	DBLP DOI BibTeX RDF
1	Mustafa K. Gurcan, Irina Ma, Hadhrami Ab. Ghani, Zhenfeng He	Complexity Reduction for Multi-hop Network End-to-End Delay Minimization.	ISCIS	2011	DBLP DOI BibTeX RDF
1	Sumet Prabhavat, Hiroki Nishiyama, Nirwan Ansari, Nei Kato	Effective Delay-Controlled Load Distribution over Multipath Networks.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	multipath forwarding, packet delay variation, load distribution, Delay minimization, packet reordering
1	Heejun Roh, Kyunghwi Kim, Wonjun Lee	Delay Minimization of Tree-Based Neighbor Discovery in Mobile Robot Networks.	WASA	2010	DBLP DOI BibTeX RDF
1	Jing Yang, Sennur Ulukus	Delay minimization with a general pentagon rate region.	ISIT	2010	DBLP DOI BibTeX RDF
1	Nicolae Cleju, Nikolaos Thomos, Pascal Frossard	Network Coding Node Placement for Delay Minimization in Streaming Overlays.	ICC	2010	DBLP DOI BibTeX RDF
1	Matthew Andrews, Antonio Fernández, Lisa Zhang, Wenbo Zhao	Routing and Scheduling for Energy and Delay Minimization in the Powerdown Model.	INFOCOM	2010	DBLP DOI BibTeX RDF
1	Francesco Chiti, Romano Fantacci, Stefano Lappoli	Contention Delay Minimization in Wireless Body Sensor Networks: A Game Theoretic Perspective.	GLOBECOM	2010	DBLP DOI BibTeX RDF
1	S. Mostafa Mostafavi, Ehsan Hamadani, Rahim Tafazzoli	Maximum Delay Minimization in Multipath Routing.	CNSR	2010	DBLP DOI BibTeX RDF
1	Alex King Yeung Cheung, Hans-Arno Jacobsen	Publisher Placement Algorithms in Content-Based Publish/Subscribe.	ICDCS	2010	DBLP DOI BibTeX RDF	publisher migration, publisher repositioning, delivery delay minimization, load minimization, Content-based publish/subscribe
1	Jing Yang, Sennur Ulukus	Delay minimization in multiple access channels.	ISIT	2009	DBLP DOI BibTeX RDF
1	Leah Epstein, Asaf Levin	A PTAS for delay minimization in establishing wireless conference calls.	Discrete Optimization	2008	DBLP DOI BibTeX RDF
1	Jason Cong, John Lee, Lieven Vandenberghe	Robust gate sizing via mean excess delay minimization.	ISPD	2008	DBLP DOI BibTeX RDF	robust gate sizing, process variation, geometric programming, conditional value-at-risk
1	Anis Ouali, Brigitte Jaumard, Gérard Hébuterne	Trade-Offs in Peer Delay Minimization for Video Streaming in P2P Systems.	CCGRID	2008	DBLP DOI BibTeX RDF	playback delay, peer-to-peer, video streaming, minimization
1	Shoufeng Lu, Ximin Liu, Shiqiang Dai	Q-Learning for Adaptive Traffic Signal Control Based on Delay Minimization Strategy.	ICNSC	2008	DBLP DOI BibTeX RDF
1	Hafiz M. Asif, Tarek R. Sheltami, Elhadi Shakshuki	Power consumption optimization and delay minimization in MANET.	MoMM	2008	DBLP DOI BibTeX RDF	ad hoc networks, routing protocols, video streaming
1	Mohamad Bouharras, Zbigniew Dziong, François Gagnon, Mohamad Haidar	Multi-objective scheduling for MUD based ad-hoc networks.	WICON	2008	DBLP DOI BibTeX RDF	fairness and wireless ad hoc networks, multiuser reception, scheduling, MAC protocol, multiuser detection
1	Zhi Zhang, Sudhir Moola, Edwin K. P. Chong	Approximate stochastic dynamic programming for opportunistic fair scheduling in wireless networks.	CDC	2008	DBLP DOI BibTeX RDF
1	Sz-Cheng Huang, Jie-Hong Roland Jiang	A dynamic accuracy-refinement approach to timing-driven technology mapping.	ICCD	2008	DBLP DOI BibTeX RDF
1	Fahimeh Jafari, Mohammad Sadegh Talebi, Ahmad Khonsari, Mohammad Hossien Yaghmaee	A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization.	ISPAN	2008	DBLP DOI BibTeX RDF	Congestion control, Network-on-Chip, iterative algorithm
1	Zhiheng Li, Dong Sun, Zixuan Zhang, Jingyan Song, Deyun Xiao	Control Mechanism Analysis of Small-Agent Networks Using a Distinguished Node Model for Urban Traffic Controls.	IEEE T. Automation Science and Engineering	2008	DBLP DOI BibTeX RDF
1	Rajeevan Chandel, Sankar Sarkar, Rajendra Prasad Agarwal	An analysis of interconnect delay minimization by low-voltage repeater insertion.	Microelectronics Journal	2007	DBLP DOI BibTeX RDF
1	Muhammad Tahir, Sudip K. Mazumder	Markov Chain Model for Performance Analysis of Transmitter Power Control in Wireless MAC Protocol: Towards Delay Minimization in Power-network Control.	AINA	2007	DBLP DOI BibTeX RDF
1	Maaike Verloop, Sem C. Borst	Heavy-Traffic Delay Minimization in Bandwidth-Sharing Networks.	INFOCOM	2007	DBLP DOI BibTeX RDF
1	Samuli Aalto, Urtzi Ayesta, Sem C. Borst, Vishal Misra, Rudesindo Núñez-Queija	Beyond processor sharing.	SIGMETRICS Performance Evaluation Review	2007	DBLP DOI BibTeX RDF	discriminatory processor sharing, in-sensitivity, multilevel processor sharing, workload, service differentiation, asymptotic analysis, queue length, sojourn time, generalized processor sharing, slowdown, delay minimization, size-based scheduling
1	Shimin Guo, Srinivasan Keshav	Fair and efficient scheduling in data ferrying networks.	CoNEXT	2007	DBLP DOI BibTeX RDF
1	Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng	Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.	ISQED	2007	DBLP DOI BibTeX RDF
1	Ryohei Suzuki, Yoshito Tobe, Kaoru Sezaki	Session Control Protocol Exploiting Controlled Mobility in Multi-Robot Sensor Networks.	LCN	2007	DBLP DOI BibTeX RDF	multi-robot sensor networks, session control protocol, sensor networks, controlled mobility
1	Bo Fu, Qiaoyan Yu, Paul Ampadu	Energy-delay minimization in nanoscale domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	delay, energy, leakage, low voltage, domino
1	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Rajiv Gandhi, Samir Khuller, Srinivasan Parthasarathy 0002, Aravind Srinivasan	Dependent rounding and its applications to approximation algorithms.	J. ACM	2006	DBLP DOI BibTeX RDF	Randomized rounding, broadcast scheduling
1	Wei-Tsong Lee, Kuo-Chih Chu, Kun-Chen Chung, Jen-Yi Pan, Pau-Choo Chung	Scheduling Delay Minimization for Non-UGS Data in Multi-Channel HFC Network.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	Interconnect delay minimization through interlayer via placement in 3-D ICs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	RC interconnects, elmore delay, 3-D ICs
1	Liang Deng, Martin D. F. Wong	Buffer insertion under process variations for delay minimization.	ICCAD	2005	DBLP BibTeX RDF
1	Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang	Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.	ISQED	2005	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Timing-driven partitioning-based placement for island style FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Leah Epstein, Asaf Levin	A PTAS for Delay Minimization in Establishing Wireless Conference Calls.	WAOA	2004	DBLP DOI BibTeX RDF
1	Hao Li, Srinivas Katkoori, Wai-Kei Mak	Power minimization algorithms for LUT-based FPGA technology mapping.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	FPGA, technology mapping, power optimization, Delay minimization
1	Mongkol Ekpanyapong, Sung Kyu Lim	Performance-driven global placement via adaptive network characterization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Vani Prasad, Madhav P. Desai	Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang	Minimum delay optimization for domino circuits - a coupling-aware approach.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Logic synthesis, coupling, domino logic, delay minimization
1	Jason Cong, Xin Yuan	Multilevel global placement with retiming.	DAC	2003	DBLP DOI BibTeX RDF	physical hierarchy, placement, retiming, deep sub-micron
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
1	Buyurman Baykal, Özgür B. Akan	A QoS-Aware Handoff using RSVP in Next Generation Wireless Networks.	ISCC	2003	DBLP DOI BibTeX RDF
1	Nageswara S. V. Rao	Netlets for End-To-End Delay Minimization in Distributed Computing Over the Internet Using Two-Paths.	IJHPCA	2002	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze, Ting-Chi Wang	Multi-Level Circuit Clustering for Delay Minimization.	IWLS	2002	DBLP BibTeX RDF
1	Shih-Wei Liao, Perry H. Wang, Hong Wang 0003, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery	Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.	PLDI	2002	DBLP DOI BibTeX RDF	chaining speculative precomputation, dependence reduction, long-range thread-based prefetching, loop rotation, post-pass, scheduling, prediction, slicing, speculation, triggering, pointer, slack, delay minimization
1	Laurent Massoulié, James Roberts	Bandwidth sharing: objectives and algorithms.	IEEE/ACM Trans. Netw.	2002	DBLP DOI BibTeX RDF	distributed random search, fixed-size window control, potential delay minimization, congestion control, max-min fairness, proportional fairness
1	Daler N. Rakhmatov, Sarma B. K. Vrudhula	Hardware-software bipartitioning for dynamically reconfigurable systems.	CODES	2002	DBLP DOI BibTeX RDF	network flows, reconfigurable systems, hardware-software partitioning
1	Jason Cong, Joey Y. Lin, Wangning Long	A new enhanced SPFD rewiring algorithm.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Shih-Hsu Huang, Yi-Siang Hsu	A timing driven approach for crosstalk minimization in gridded channel routing.	APCCAS	2002	DBLP DOI BibTeX RDF
1	Rajiv Gandhi, Samir Khuller, Srinivasan Parthasarathy 0002, Aravind Srinivasan	Dependent Rounding in Bipartite Graphs.	FOCS	2002	DBLP DOI BibTeX RDF
1	Ling Wang, Henry Selvaraj	Performance Driven Circuit Clustering and Partitioning.	ITCC	2002	DBLP DOI BibTeX RDF	Cutsize, Clustering, Delay, Partitioning
1	Chris C. N. Chu, D. F. Wong	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
1	Yu-Yen Mo, Chris C. N. Chu	Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Javed I. Khan	Active Streaming in Transport Delay Minimization. (PDF / PS)	ICPP Workshops	2000	DBLP DOI BibTeX RDF	proactive Internet caching, Multimedia, streaming, pre-fetching, delay optimization
1	Jason Cong, Yean-Yow Hwang	Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	computer-aided design of VSLI, FPGA, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, logic optimization, delay minimization
1	Jason Cong, Sung Kyu Lim, Chang Wu	Performance driven multi-level and multiway partitioning with retiming.	DAC	2000	DBLP DOI BibTeX RDF
1	Jason Cong, Songjie Xu	Performance-driven technology mapping for heterogeneous FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Rupesh S. Shelar, Madhav P. Desai, H. Narayanan	Decomposition of Finite State Machines for Area, Delay Minimization.	ICCD	1999	DBLP DOI BibTeX RDF	Orthogonal Partitioning, Finite State Machines, Decomposition, State Assignment, Area Minimization
1	Chris C. N. Chu, Martin D. F. Wong	A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Chris C. N. Chu, Martin D. F. Wong	An efficient and optimal algorithm for simultaneous buffer and wire sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Amir H. Salek, Jinan Lou, Massoud Pedram	An integrated logical and physical design flow for deep submicron circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Jason Cong, Songjie Xu	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs.	DAC	1998	DBLP DOI BibTeX RDF	technology mapping, programmable logic devices, PLA-style logic blocks
1	Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar	Delay-Optimal Technology Mapping by DAG Covering.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
1	Jason Cong, Songjie Xu	Technology Mapping for FPGAs with Embedded Memory Blocks.	FPGA	1998	DBLP DOI BibTeX RDF
1	Luca Benini, Patrick Vuillod, Giovanni De Micheli	Iterative remapping for logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Hannah Honghua Yang, Martin D. F. Wong	Circuit clustering for delay minimization under area and pin constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
1	Robert N. Smith, Sourav Bhattacharya	Firewall placement in a large network topology.	FTDCS	1997	DBLP DOI BibTeX RDF	firewall placement heuristics, large network topology, multi-user distributed information environment, firewall cascade, potential attack point, comprehensive security protection, end-to-end security protection, simulation, performance, network security, completeness, authorisation, operations research, cost optimization, delay minimization, sensitive data, confidence degree
1	Ronald Beaubrun, Samuel Pierre	A routing algorithm for distributed communication networks. (PDF / PS)	LCN	1997	DBLP DOI BibTeX RDF	distributed communication networks, link congestion, robust routing strategy, MINDEL, distributed network links, packet delay minimization, routing algorithm, wide area networks, wide area networks, high-speed networks, network traffic, LAN, polynomial complexity
1	Min-You Wu, Wei Shu, Karthikeyan Samuthiram	Optimal Scheduling for Normal and Interactive Operations in Parallel Video Servers. (PDF / PS)	COMPSAC	1997	DBLP DOI BibTeX RDF	normal playout, interactive operations, scheduling, performance, parallel video server
1	M. L. G. Smeets, Emile H. L. Aarts, Gerben Essink, Erwin A. de Kock	Delay management for programmable video signal processors.	ED&TC	1997	DBLP DOI BibTeX RDF
1	S. Turgis, Jean Michel Daga, J. M. Portal, Daniel Auvergne	Internal power modelling and minimization in CMOS inverters.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Jason Cong, Patrick H. Madden	Performance-driven routing with multiple sources.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Jason Cong, Yuzheng Ding	Combinational logic synthesis for LUT based field programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	FPGA, routing, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, power minimization, logic optimization, delay modeling, delay minimization, computer-aided design of VLSI, area minimization
1	Takumi Okamoto, Jason Cong	Buffered Steiner tree construction with wire sizing for interconnect layout optimization.	ICCAD	1996	DBLP DOI BibTeX RDF	Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing
1	Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin	Combining technology mapping and placement for delay-minimization in FPGA designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash	Efficient use of large don't cares in high-level and logic synthesis.	ICCAD	1995	DBLP DOI BibTeX RDF
1	Sourav Bhattacharya, Aloke Guha, Allalaghatta Pavan, David Hung-Chang Du	Optimal multihop routing. An iterative approach to TWDM embedding. (PDF / PS)	LCN	1995	DBLP DOI BibTeX RDF	TWDM embedding, time-wave division multiplexed, lightwave networks, time slot assignments, graph unfolding, routing delay, performance, wavelength division multiplexing, telecommunication network routing, time division multiplexing, weighted graphs, optimal routing, shortest path routing, optical fibre LAN, multihop routing, iterative approach
1	Jason Cong, Yuzheng Ding	On nominal delay minimization in LUT-based FPGA technology mapping.	Integration	1994	DBLP DOI BibTeX RDF