Search results for "Denis Flandre"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Julien De Vos, Denis Flandre, David Bol	Pushing Adaptive Voltage Scaling Fully on Chip.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Pierre-Antoine Haddad, Geoffroy Gosset, Denis Flandre	Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Valeria Kilchytska, Joaquín Alvarado, S. Put, Nadine Collaert, Eddy Simoen, Cor Claeys, O. Militaru, G. Berger, Denis Flandre	High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs.	Microelectronics Reliability	2012	DBLP DOI BibTeX RDF
1	David Bol, Julien De Vos, Cédric Hocquet, Francois Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat	A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes.	ISSCC	2012	DBLP DOI BibTeX RDF
1	C. Roda Neve, Valeria Kilchytska, Joaquín Alvarado, D. Lederer, O. Militaru, Denis Flandre, Jean-Pierre Raskin	Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert	Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.	J. Cryptographic Engineering	2011	DBLP DOI BibTeX RDF
1	Mathieu Renauld, Dina Kamel, François-Xavier Standaert, Denis Flandre	Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box.	CHES	2011	DBLP DOI BibTeX RDF
1	Mathieu Renauld, François-Xavier Standaert, Nicolas Veyrat-Charvillon, Dina Kamel, Denis Flandre	A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices.	EUROCRYPT	2011	DBLP DOI BibTeX RDF
1	David Bol, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Joaquín Alvarado, E. Boufouss, Valeria Kilchytska, Denis Flandre	Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Ilham Hassoune, Denis Flandre, Ian O'Connor, Jean-Didier Legat	ULPFA: A New Efficient Design of a Power-Aware Full Adder.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat	Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
1	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Interests and Limitations of Technology Scaling for Subthreshold Logic.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
1	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
1	Dina Kamel, François-Xavier Standaert, Denis Flandre	Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Rodrigo Trevisoli Doria, Antonio Cerdeira, Jean-Pierre Raskin, Denis Flandre, Marcelo Antonio Pavanello	Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF
1	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Impact of Technology Scaling on Digital Subthreshold Circuits.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Ahmed El Oualkadi, Denis Flandre	Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
1	Joaquín Alvarado, Antonio Cerdeira, Valeria Kilchytska, Denis Flandre	Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs.	Microelectronics Journal	2007	DBLP DOI BibTeX RDF
1	David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.	Multiple-Valued Logic and Soft Computing	2007	DBLP BibTeX RDF
1	Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat	Dynamic differential self-timed logic families for robust and low-power security ICs.	Integration	2007	DBLP DOI BibTeX RDF
1	Marcelo Antonio Pavanello, Paula Ghedini Der Agopian, João Antonio Martino, Denis Flandre	Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications.	Microelectronics Journal	2006	DBLP DOI BibTeX RDF
1	Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat	Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks.	Microelectronics Journal	2006	DBLP DOI BibTeX RDF
1	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre	Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS.	Microelectronics Journal	2006	DBLP DOI BibTeX RDF
1	David Levacq, Vincent Dessard, Denis Flandre	Ultra-low power flip-flops for MTCMOS circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre	Power-delay product minimization in high-performance 64-bit carry-select adders.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Amaury Nève, Denis Flandre, Jean-Jacques Quisquater	SOI Technology for Future High-Performance Smart Cards.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Magali Estrada, A. Afzalian, Denis Flandre, Antonio Cerdeira, H. Baez, A. de Lucca	FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si: H photodiode.	Microelectronics Reliability	2003	DBLP DOI BibTeX RDF
1	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, S. Adriaensen, Denis Flandre	Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
1	Amaury Nève, Denis Flandre	Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies.	VLSI-SOC	2001	DBLP BibTeX RDF

Publications of "Denis Flandre" ( http://dblp.L3S.de/Authors/Denis_Flandre )