|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1 occurrences of 1 keywords
|
|
|
|
|
Results
Found 8 publication records. Showing 8 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko |
A 28 nm 0.6 V Low Power DSP for Mobile Applications.  |
J. Solid-State Circuits  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan |
The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko |
A 28nm 0.6V low-power DSP for mobile applications. |
ISSCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan |
Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Rithe, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan |
Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | G. Singer, Philippe Magarshack, Dennis Buss, F.-C. Hsu, H.-K. Kang |
"The IC nanometer race -- what will it take to win?". |
DAC |
2006 |
DBLP DOI BibTeX RDF |
hardware |
| 1 | Dennis Buss |
Technology and design challenges for mobile communication and computing products. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper |
Yield of VLSI circuits: myths vs. reality (panel). |
DAC |
1986 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #8 of 8 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")