Search results for "Design-for-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Waleed K. Al-Assadi, Sindhu Kakarla	Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT)
3	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
3	Marina Santo Zarnik, Franc Novak, Srecko Macek	Design for Test of Crystal Oscillators: A Case Study.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	crystal oscillators, fault diagnosis, analog circuits, design-for-test
2	Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang	Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.	ASP-DAC	2009	DBLP DOI BibTeX RDF	?? modulation, analog/mixed-signal testing, integrator leakage, diagnosis, design-for-test (DfT)
2	Amir Zjajo, José Pineda de Gyvez	Calibration and Debugging of Multi-step Analog to Digital Converters.	DELTA	2008	DBLP DOI BibTeX RDF	multi-step ADC, debugging, calibration, design-for-test
2	Ben Bennetts	Electronics Design-for-Test: Past, Present and Future.	European Test Symposium	2007	DBLP DOI BibTeX RDF
2	Shin-Yi Lin, Chih-Tsun Huang	A High-Throughput Low-Power AES Cipher for Network Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, low-power AES cipher, two-stage pipeline, CCM mode, design-for-test circuitry, 4.27 Gbits/s, 333 MHz, 40.9 mW, CMOS technology, network applications
2	Bo Yang, Kaijie Wu, Ramesh Karri	Secure Scan: A Design-for-Test Architecture for Crypto Chips.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jiun-Lang Huang	On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	jitter measurement, random jitter, analog/mixed-signal testing, design-for-test
2	Bo Yang, Kaijie Wu, Ramesh Karri	Secure scan: a design-for-test architecture for crypto chips.	DAC	2005	DBLP DOI BibTeX RDF	crypto hardware, scan-based DFT, security, testability
2	C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar	A Framework for Distributed and Hierarchical Design-for-Test.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Carsten Wegener, Michael Peter Kennedy	Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	model-based ADC test, device interface parasitics, Design-for-Test
2	Oussama Laouamri, Chouki Aktouf	Towards a Complete SNMP-Based Supervision of System-on-Chips.	J. Network Syst. Manage.	2005	DBLP DOI BibTeX RDF	P1500 wrapper, System-on-chips, Network management, SNMP, Design-for-test
2	C. P. Ravikumar, Graham Hetherington	A Holistic Parallel and Hierarchical Approach towards Design-For-Test.	ITC	2004	DBLP DOI BibTeX RDF	Experiments and Case Studies, Practical Test Engineering
2	Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal	A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis.	ITC	2004	DBLP DOI BibTeX RDF
2	José Luis Huertas	Test and design-for-test of mixed-signal integrated circuits.	SBCCI	2004	DBLP DOI BibTeX RDF
2	John P. Hayes, Ilia Polian, Bernd Becker	Testing for Missing-Gate Faults in Reversible Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	missing gate faults, fault models, design for test, quantum circuits, Reversible circuits
2	José Vicente Calvano, Vladimir Castro Alves, Antônio C. Mesquita, Marcelo Lubaszewski	Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus.	VTS	2002	DBLP DOI BibTeX RDF	BIST, design for test, analog test, mixed-signal test
2	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
2	Florentin Ipate, Mike Holcombe	Testing Conditions for Communicating Stream X-machine Systems.	Formal Asp. Comput.	2002	DBLP DOI BibTeX RDF	Communicating (extended) fsm, Communicating (stream) X-machines, Design for test-conditions, Testing
2	Jeroen Voeten, Harald P. E. Vranken	Behavior-Preserving Transformations for Design-for-Test.	EUROMICRO	2000	DBLP DOI BibTeX RDF
2	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
2	Jon Turino	Design for Test and Time to Market: A Personal Perspective.	IEEE Design & Test of Computers	1999	DBLP DOI BibTeX RDF
2	Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi	Pseudoduplication - An ACOB Technique for Single-Ended Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	pseudoduplication, ACOB, analog circuit observer block, single-ended switched capacitor filter, data duplication code, simulation, fault detection, layout, design for test, switched capacitor filters
2	Johan Verfaillie, Didier Haspeslagh	A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	mixed-signal DFT, mixed-signal boundary scan, modular mixed-signal test
2	Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer	A Design For Test Perspective on I/O Management. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	I/O pads, High Level Synthesis, Design For Test, Boundary Scan
2	Javier Argüelles, Salvador Bracho	Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	mixed-signal IC testing, design for test in mixed-signal IC, built-in current sensors
2	Michel Renovell, Florence Azaïs, Yves Bertrand	A design-for-test technique for multistage analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing
2	Hon Fung Li, P. N. Lam	A protocol extraction strategy for control point insertion in design for test of transition signaling circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	protocol extraction strategy, control point insertion, transition signaling circuits, hazard-free test, safe behaviors, gap detection, gap matching, single input pad, protocols, logic testing, design for testability, asynchronous circuits, asynchronous circuits, design for test, test length, area overhead
2	J. Arguelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho	Iddt testing of continuous-time filters.	VTS	1995	DBLP DOI BibTeX RDF	continuous time filters, continuous-time filters, design-for-test methodology, dynamic supply current consumption, dynamic current, partitioning methodology, test reliability, built-in self test, integrated circuit testing, design for testability, automatic testing, CMOS, automatic test equipment, built-in current sensor, CMOS analogue integrated circuits
2	Diego Vázquez, Adoración Rueda, José L. Huertas	A solution for the on-line test of analog ladder filters.	VTS	1995	DBLP DOI BibTeX RDF	ladder filters, analog ladder filters, stability problems, design for test methodology, solution feasibility, analogue ICs, integrated circuit testing, design for testability, on-line testing, analogue integrated circuits, active filters, active filters, circuit stability
2	Farzad Zarrinfar	Economics of "design for test" to remain competitive in the 90s.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	Bed-of-nails method, DFT strategy, value adders
2	R. G. (Ben) Bennitts	Progress in Design for Test: A Personal View.	IEEE Design & Test of Computers	1994	DBLP DOI BibTeX RDF
2	Franc Novak, Igor Mozetic, Marina Santo Zarnik, Anton Biasizzo	Enhancing design-for-test for active analog filters by using CLP.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF
2	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
1	James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada	A design-for-test apparatus for measuring on-chip temperature with fine granularity.	ISQED	2012	DBLP DOI BibTeX RDF
1	Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky	Design for test and reliability in ultimate CMOS.	DATE	2012	DBLP BibTeX RDF
1	Mainak Banga, Michael S. Hsiao	ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs.	HOST	2011	DBLP DOI BibTeX RDF
1	Mainak Banga, Nikhil P. Rahagude, Michael S. Hsiao	Design-for-test methodology for non-scan at-speed testing.	DATE	2011	DBLP BibTeX RDF
1	Yolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho	Design-for-Test method for high-speed ADCs: Behavioral description and optimization.	DDECS	2011	DBLP DOI BibTeX RDF
1	Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu	DfT Architecture for 3D-SICs with Multiple Towers.	European Test Symposium	2011	DBLP DOI BibTeX RDF	three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via
1	S. Saqib Khursheed, Sheng Yang, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn	Improved DFT for Testing Power Switches.	European Test Symposium	2011	DBLP DOI BibTeX RDF	power switch, leakage power management, test time overhead, DFT, design for test, Sleep transistor
1	Qi Fan	General Design for Test Guidelines for RF IC.	J. Electronic Testing	2010	DBLP BibTeX RDF
1	Yizi Xing, Liquan Fang	Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCs.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Jaizki Mendizabal, Unai Alvarado, Iñigo Adin, Guillermo Bistue, Juan Meléndez, Roc Berenguer	Design for test of a low power multi-standard GPS/GALILEO RF front-end.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin	Efficient fault simulation on many-core processors.	DAC	2010	DBLP DOI BibTeX RDF	PPSFP, parallel fault simulation, many-core processors
1	Rahul Bhattachrya, Santosh Biswas, Siddhartha Mukhopadhyay	FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	ams testing, concurrent test development, behavioral modeling
1	Rebecca Wirfs-Brock	Design for Test.	IEEE Software	2009	DBLP DOI BibTeX RDF
1	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li	Turbo1500: Core-Based Design for Test and Diagnosis.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang	Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	A new design-for-test technique for SRAM core-cell stability faults.	DATE	2009	DBLP BibTeX RDF
1	Anton Chichkov	Challenges for test and design for test.	DDECS	2009	DBLP DOI BibTeX RDF
1	Zhen Chen, Dong Xiang, Boxue Yin	A power-effective scan architecture using scan flip-flops clustering and post-generation filling.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
1	Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich	Test Encoding for Extreme Response Compaction.	European Test Symposium	2009	DBLP DOI BibTeX RDF	Embedded Diagnosis, Design for Test, Test Compression, Response Compaction
1	Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur	Proactive management of X's in scan chains for compression.	ISQED	2009	DBLP DOI BibTeX RDF
1	Waleed K. Al-Assadi, Sindhu Kakarla	Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.	ITC	2008	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li	Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.	ITC	2008	DBLP DOI BibTeX RDF
1	Kamran Zarrineh	Design for Test Challenges of High Performance/Low Power Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
1	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding	Scan chain clustering for test power reduction.	DAC	2008	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
1	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
1	Matthew G. Stout, Kenneth P. Tumin	Innovative Test Solutions for Pin-Limited Microcontrollers.	ISQED	2008	DBLP DOI BibTeX RDF	Freescale, Stout, Tumin, test, testing, DFT, scan, microcontroller, design-for-test, pins
1	Naoki Iwasaki, Katsumi Wasaki	A Meta Hardware Description Language Melasy for Model-Checking Systems.	ITNG	2008	DBLP DOI BibTeX RDF	Hardware/Software co-design and co-verification, Model Checking, Haskell, Design-for-test, Hardware Compilers
1	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Controllability of Static CMOS Circuits for Timing Characterization.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Design for test, Delay fault testing, Scan design
1	Stephen K. Sunter, Aubin Roy	Noise-Insensitive Digital BIST for any PLL or DLL.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL
1	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
1	Syed M. Alam, Mike Ignatowski, Yuan Xie	Technology, CAD tools, and designs for emerging 3D integration technology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D CAD, 3D IC
1	Gordon W. Roberts	Test Methods For Sigma-Delta Data Converters and Related Devices.	SBCCI	2008	DBLP DOI BibTeX RDF	sigma-delta converter, mixed-signal testing
1	Amir Zjajo, José Pineda de Gyvez	Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters.	DATE	2008	DBLP DOI BibTeX RDF
1	Frantisek Reznicek	Mixed-Signal DFT for fully testable ASIC.	DDECS	2008	DBLP DOI BibTeX RDF
1	Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu	Minimization of CTS of k-CNOT Circuits for SSF and MSF Model.	DFT	2008	DBLP DOI BibTeX RDF
1	Saurabh Jain, W. Robert Daasch, David Armbrust	Analyzing the Impact of Fault Tolerant BIST for VLSI Design.	DFT	2008	DBLP DOI BibTeX RDF
1	Nathaniel August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intels Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
1	Anshuman Chandra, Rohit Kapur	Interval Based X-Masking for Scan Compression Architectures.	ISQED	2008	DBLP DOI BibTeX RDF	X masking, test, compression, DFT, scan
1	Byoungho Kim, Nash Khouzam, Jacob A. Abraham	Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.	VTS	2008	DBLP DOI BibTeX RDF	Loopback Test, Aperture Jitter, Digital-to-Analog Converter, Analog-to-Digital Converter, ADC, Mixed-Signal Testing, DAC
1	Roberto Gómez, Alejandro Girón, Víctor H. Champac	A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Interconnection opens, Boolean testing, Favorable logic conditions, Test generation methodology, Coupling capacitances
1	Antonio Zenteno Ramirez, Guillermo Espinosa, Víctor H. Champac	Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Frank Frederick, Teresa L. McLaurin	Design for test features of the ARM clock control macro.	ITC	2007	DBLP DOI BibTeX RDF
1	Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach	Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.	NOCS	2007	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
1	J. M. Gilbert, Ian M. Bell	The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	test escapes, test capability, electronics design, quality, test coverage, design for test, process capability
1	Oussama Laouamri, Chouki Aktouf	Remote testing and diagnosis of System-on-Chips using network management frameworks.	DATE	2007	DBLP DOI BibTeX RDF
1	Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro	Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model.	DATE	2007	DBLP DOI BibTeX RDF
1	Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters	Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.	DATE	2007	DBLP DOI BibTeX RDF
1	P. Yeung, A. Torres, P. Batra	Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor.	DATE	2007	DBLP DOI BibTeX RDF
1	Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers	Synthesis of irregular combinational functions with large don't care sets.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	logic synthesis, incompletely specified functions
1	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira	Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.	DFT	2007	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Erik Schüler, Marcelo Negreiros, Pascal Nouet, Luigi Carro	A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Paul Falkenstern, Yuan Xie	Scan chain design for three-dimensional integrated circuits (3D ICs).	ICCD	2007	DBLP DOI BibTeX RDF
1	Byoungho Kim, Zhenhai Fu, Jacob A. Abraham	Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications.	VTS	2007	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Robert C. Aitken, S. Kundu	Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Venkat Satagopan, Bonita Bhaskaran, Waleed Al-Assadi, Scott C. Smith, Sindhu Kakarla	DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park	An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing
1	Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez	Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Analogue fault simulation, Catastrophic and parametric faults, Process deviations, Analogue test, Statistical modeling
1	Jose M. M. Ferreira, Manuel G. O. Gericota, Antonio M. Cardoso	An integrated framework to support remote IEEE 1149.1 / 1149.4 design for test experiments.	iJOE	2006	DBLP BibTeX RDF
1	Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand	Design-for-Test of Asynchronous Networks-on-Chip.	DDECS	2006	DBLP BibTeX RDF
1	Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei	Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.	DAC	2006	DBLP DOI BibTeX RDF	design for test, test response compaction
1	Doug Josephson	The good, the bad, and the ugly of silicon debug.	DAC	2006	DBLP DOI BibTeX RDF	design for test and debug, debug, validation, characterization
1	Ad M. G. Peeters	Clockless IC design using handshake technology.	ISPD	2006	DBLP DOI BibTeX RDF