| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan |
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
STEP: a unified design methodology for secure test and IP core protection. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski |
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. |
J. Low Power Electronics |
2011 |
DBLP BibTeX RDF |
|
| 1 | Costas Argyrides, Raul Chipana, Fabian Vargas, Dhiraj K. Pradhan |
Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction. |
IEEE Transactions on Reliability |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishram Mishra, Jimson Mathew, Dhiraj K. Pradhan |
Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks. |
IJSNet |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak |
Matrix Codes for Reliable and Cost Efficient Memory Chips. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty |
A Routing-Aware ILS Design Technique. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan |
Fault Tolerant Single Error Correction Encoders. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty |
BCH code based multiple bit error correction in finite field multiplier circuits. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan |
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. |
ECCTD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski |
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos |
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Taskin Koçak, Dhiraj K. Pradhan |
Introduction to design techniques for energy harvesting. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Dhiraj K. Pradhan |
ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management. |
JETC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan |
Secure Testable S-box Architecture for Cryptographic Hardware Implementation. |
Comput. J. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan |
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan |
A Galois field-based logic synthesis with testability. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan |
Test Generation in Systolic Architecture for Multiplication Over GF(2 m). |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
Layout-aware Illinois Scan design for high fault coverage coverage. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan |
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan |
On the design of different concurrent EDC schemes for S-Box and GF(p). |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Nikolaos Mavrogiannakis, Dhiraj K. Pradhan |
Improved Yield in Nanotechnology Circuits Using Non-square Meshes. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan |
Improving reliability for bit parallel finite field multipliers using Decimal Hamming. |
EWDTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir |
On the synthesis of attack tolerant cryptographic hardware. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
nano-CMOS, power, leakage, SRAM, static noise margin |
| 1 | Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan |
Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. |
PerCom Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin |
| 1 | Dmitri Maslov, Jimson Mathew, Donny Cheung, Dhiraj K. Pradhan |
An O(m2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2m)a. |
Quantum Information & Computation |
2009 |
DBLP BibTeX RDF |
|
| 1 | Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan |
Single error correctable bit parallel multipliers over GF(2m). |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Ahmad A. Al-Yamani, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan |
Increasing memory yield in future technologies through innovative design. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro |
Reliability aware yield improvement technique for nanotechnology based circuits. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
reliability, nanotechnology, yield improvement |
| 1 | Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan |
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew |
Single ended 6T SRAM with isolated read-port for low-power embedded systems. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan |
C-testable S-box implementation for secure advanced encryption standard. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro |
A fast error correction technique for matrix multiplication algorithms. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongwei Zhu, Ilie I. Luican, Florin Balasa, Dhiraj K. Pradhan |
Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir |
C-testable bit parallel multipliers over GF(2m). |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable |
| 1 | Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir |
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew |
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan |
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan |
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis. |
IET Computers & Digital Techniques |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Bharat Joshi, Dhiraj K. Pradhan, Jack Stiffler |
Fault-Tolerant Computing. |
Wiley Encyclopedia of Computer Science and Engineering |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan |
Area Reliability Trade-Off in Improved Reed Muller Coding. |
SAMOS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan |
On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. |
TQC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Carlos Arthur Lang Lisbôa, Costas Argyrides, Dhiraj K. Pradhan, Luigi Carro |
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
radiation effects, long transients, recomputation granularity, fault tolerance |
| 1 | Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan |
A Galois Field Based Logic Synthesis Approach with Testability. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan |
Single Error Correcting Finite Field Multipliers Over GF(2m). |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes |
| 1 | Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan |
Design of Reversible Finite Field Arithmetic Circuits with Error Detection. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan |
A nano-CMOS process variation induced read failure tolerant SRAM cell. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan |
Fault tolerant bit parallel finite field multipliers using LDPC codes. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Fabian Vargas, Marlon Moraes, Dhiraj K. Pradhan |
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan |
Fault Tolerant Reversible Finite Field Arithmetic Circuits. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan |
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
Failure analysis for ultra low power nano-CMOS SRAM under process variations. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan |
Pseudo parallel architecture for AES with error correction. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Abusaleh M. Jabir, Dhiraj K. Pradhan |
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Finite or Galois fields, polynomials, decision diagrams, coefficients |
| 1 | Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh |
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Finite or Galois Fields, Characteristic and Encoded Characteristic Functions, Simulation, Evaluation, Verification, Decision Diagrams |
| 1 | Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan |
Single Event Upset Detection and Correction. |
ICIT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan |
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew |
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan |
A soft error robust and power aware memory design. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
robustness, memory, soft error, power aware |
| 1 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan |
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan |
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). |
VTS |
2007 |
DBLP DOI BibTeX RDF |
cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable |
| 1 | Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan |
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan |
Multiple Upsets Tolerance in SRAM Memory. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan |
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew |
CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan |
On the Hardware Reduction of z-Datapath of Vectoring CORDIC. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew |
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan |
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Dhiraj K. Pradhan |
Highly Reliable Power Aware Memory Design. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan |
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Ahmad A. Al-Yamani, Dhiraj K. Pradhan |
High defect tolerant low cost memory chips. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Costas Argyrides, Dhiraj K. Pradhan |
Improved decoding algorithm for high reliable reed muller coding. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan |
A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan |
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunsheng Liu, Zach Link, Dhiraj K. Pradhan |
Reuse-based test access and integrated test scheduling for network-on-chip. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew |
An efficient technique for synthesis and optimization of polynomials in GF(2m). |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Dhiraj K. Pradhan, Chunsheng Liu |
EBIST: a novel test generator with built-in fault detection capability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan |
Comparative study of CA with phase shifters and GLFSRs. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea |
Recent Advances in Verification, Equivalence Checking and SAT-Solvers. (PDF / PS) |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir |
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhasis Bhattacharjee, Dhiraj K. Pradhan |
LPRAM: a novel low-power high-performance RAM design with testability and scalability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan |
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sathiamoorthy Subbarayan, Dhiraj K. Pradhan |
NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances. |
SAT |
2004 |
DBLP BibTeX RDF |
|
| 1 | Sathiamoorthy Subbarayan, Dhiraj K. Pradhan |
NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances. |
SAT (Selected Papers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhasis Bhattacharjee, Dhiraj K. Pradhan |
LPRAM: a low power DRAM with testability. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Abusaleh M. Jabir, Dhiraj K. Pradhan |
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mitrajit Chatterjee, Dhiraj K. Pradhan |
A BIST Pattern Generator Design for Near-Perfect Fault Coverage. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC |
| 1 | Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty |
EBIST: A Novel Test Generator with Built-In Fault Detection Capability. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Elango Ganesan, Dhiraj K. Pradhan |
Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma |
ATPG for Design Errors-Is It Possible? |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Dhiraj K. Pradhan |
Logic Insertion to Speed-Up Logic Verification: A Recent Development. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan |
Buffer Assignment Algorithms on Data Driven ASICs. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture |
| 1 | Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan |
VERILAT: verification using logic augmentation and transformations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Dhiraj K. Pradhan, Mitrajit Chatterjee |
GLFSR-a new test pattern generator for built-in-self-test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
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