Search results for "Doug Burger"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger	Architecture support for disciplined approximate programming.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger	Dark silicon and the end of multicore scaling.	ISCA	2011	DBLP DOI BibTeX RDF
1	Emmanouil Koukoumidis, Dimitrios Lymberopoulos, Karin Strauss, Jie Liu, Doug Burger	Pocket cloudlets.	ASPLOS	2011	DBLP DOI BibTeX RDF
1	Per Stenström, Doug Burger, Wen-mei W. Hwu, Vipin Kumar, Kunle Olukotun, David A. Padua, Burton Smith	Panel Statement.	IPDPS	2011	DBLP DOI BibTeX RDF
1	Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger	Preventing PCM banks from seizing too much power.	MICRO	2011	DBLP DOI BibTeX RDF
1	Behnam Robatmili, Madhu Saravana Sibi Govindan, Doug Burger, Stephen W. Keckler	Exploiting criticality to reduce bottlenecks in distributed uniprocessors.	HPCA	2011	DBLP DOI BibTeX RDF
1	Andrew Putnam, Aaron Smith, Doug Burger	Dynamic vectorization in the E2 dynamic multicore architecture.	SIGARCH Computer Architecture News	2010	DBLP DOI BibTeX RDF
1	Benjamin C. Lee, Ping Zhou, Jun Yang 0002, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger	Phase-Change Technology and the Future of Main Memory.	IEEE Micro	2010	DBLP DOI BibTeX RDF	energy efficiency, memory architecture, DRAM, technology scaling, phase-change memory, PCM
1	James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi	The Future of Architectural Simulation.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Phase change memory architecture and the quest for scalability.	Commun. ACM	2010	DBLP DOI BibTeX RDF
1	Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger	Use ECP, not ECC, for hard failures in resistive memories.	ISCA	2010	DBLP DOI BibTeX RDF	hard failures, resistive memories, memory, error correction, phase change memory
1	Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi	Using dead blocks as a virtual victim cache.	PACT	2010	DBLP DOI BibTeX RDF
1	Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, Thomas Moscibroda	Dynamically replicated memory: building reliable systems from nanoscale resistive memories.	ASPLOS	2010	DBLP DOI BibTeX RDF	write endurance, phase-change memory
1	Matthew E. Taylor, Katherine E. Coons, Behnam Robatmili, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley	Evolving Compiler Heuristics to Manage Communication and Contention.	AAAI	2010	DBLP BibTeX RDF
1	Renée St. Amant, Daniel A. Jiménez, Doug Burger	Mixed-Signal Approximate Computation: A Neural Predictor Case Study.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Architecting phase change memory as a scalable dram alternative.	ISCA	2009	DBLP DOI BibTeX RDF	dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance
1	Nitya Ranganathan, Doug Burger, Stephen W. Keckler	Analysis of the TRIPS prototype block predictor.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Madhu Saravana Sibi Govindan, Stephen W. Keckler, Doug Burger	End-to-end validation of architectural power models.	ISLPED	2009	DBLP DOI BibTeX RDF	architectural power models, measurement, validation
1	Jeremy Condit, Edmund B. Nightingale, Christopher Frost, Engin Ipek, Benjamin C. Lee, Doug Burger, Derrick Coetzee	Better I/O through byte-addressable, persistent memory.	SOSP	2009	DBLP DOI BibTeX RDF	performance, file systems, phase change memory
1	Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeffrey R. Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James H. Burrill, Stephen W. Keckler, Doug Burger, Kathryn S. McKinley	An evaluation of the TRIPS computer system.	ASPLOS	2009	DBLP DOI BibTeX RDF	trips
1	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible core chip multiprocessors.	SIGARCH Computer Architecture News	2008	DBLP DOI BibTeX RDF
1	Franziska Roesner, Doug Burger, Stephen W. Keckler	Counting Dependence Predictors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Katherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley	Feature selection and policy optimization for distributed instruction placement using reinforcement learning.	PACT	2008	DBLP DOI BibTeX RDF	compiler heuristics, genetic algorithms, neural networks, machine learning, instruction scheduling
1	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
1	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Strategies for mapping dataflow blocks to distributed hardware.	MICRO	2008	DBLP DOI BibTeX RDF
1	Renée St. Amant, Daniel A. Jiménez, Doug Burger	Low-power, high-performance analog neural branch prediction.	MICRO	2008	DBLP DOI BibTeX RDF
1	Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger	Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.	MICRO	2008	DBLP DOI BibTeX RDF
1	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Register Bank Assignment for Spatially Partitioned Processors.	LCPC	2008	DBLP DOI BibTeX RDF
1	Jeffrey R. Diamond, Behnam Robatmili, Stephen W. Keckler, Robert A. van de Geijn, Kazushige Goto, Doug Burger	High performance dense linear algebra on a spatially distributed processor.	PPOPP	2008	DBLP DOI BibTeX RDF	gotoblas, grid processors, hybrid dataflow, matrix multiply, tile based architecture, instruction level parallelism, on-chip networks, dense linear algebra
1	Nicholas Nethercote, Doug Burger, Kathryn S. McKinley	Convergent Compilation Applied to Loop Unrolling.	T. HiPEAC	2007	DBLP DOI BibTeX RDF
1	Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	On-Chip Interconnection Networks of the TRIPS Chip.	IEEE Micro	2007	DBLP DOI BibTeX RDF	communication, networking, distributed architectures, packet-switching networks, multicore architectures, on-chip interconnection networks
1	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA Substrate for Flexible CMP Cache Sharing.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Multiprocessor systems, cache memories, adaptable architectures
1	Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler	Late-binding: enabling unordered load-store queues.	ISCA	2007	DBLP DOI BibTeX RDF	network flow control, memory disambiguation, late binding
1	Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of a Dynamically Routed Processor Operand Network.	NOCS	2007	DBLP DOI BibTeX RDF
1	Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler	Composable Lightweight Processors.	MICRO	2007	DBLP DOI BibTeX RDF
1	Aaron Smith, Jon Gibson, Bertrand A. Maher, Nicholas Nethercote, Bill Yoder, Doug Burger, Kathryn S. McKinley, James H. Burrill	Compiling for EDGE Architectures.	CGO	2006	DBLP DOI BibTeX RDF
1	Ramadass Nagarajan, Xia Chen, Robert G. McDonald, Doug Burger, Stephen W. Keckler	Critical path analysis of the TRIPS architecture.	ISPASS	2006	DBLP DOI BibTeX RDF
1	Katherine E. Coons, Xia Chen, Doug Burger, Kathryn S. McKinley, Sundeep K. Kushwaha	A spatial path scheduling algorithm for EDGE architectures.	ASPLOS	2006	DBLP DOI BibTeX RDF	EDGE architecture, path scheduling, simulated annealing, instruction scheduling
1	Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley	Dataflow Predication.	MICRO	2006	DBLP DOI BibTeX RDF
1	Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley	Merging Head and Tail Duplication for Convergent Hyperblock Formation.	MICRO	2006	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.	MICRO	2006	DBLP DOI BibTeX RDF
1	Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of On-Chip Network Architectures.	ICCD	2006	DBLP BibTeX RDF
1	Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler	Design and Implementation of the TRIPS Primary Memory System.	ICCD	2006	DBLP BibTeX RDF
1	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore	TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.	TACO	2004	DBLP DOI BibTeX RDF	scalable and high-performance computing, Computer architecture, configurable computing
1	Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi	Speculative Incoherent Cache Protocols.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler	Scalable Hardware Memory Disambiguation for High-ILP Processors.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode	Scaling to the End of Silicon with EDGE Architectures.	IEEE Computer	2004	DBLP DOI BibTeX RDF
1	Doug Burger, James R. Goodman	Billion-Transistor Architectures: There and Back Again.	IEEE Computer	2004	DBLP DOI BibTeX RDF
1	Doug Burger, Todd M. Austin, Stephen W. Keckler	Recent extensions to the SimpleScalar tool suite.	SIGMETRICS Performance Evaluation Review	2004	DBLP DOI BibTeX RDF
1	Doug Burger, Anand Sivasubramaniam	Tools for computer architecture research.	SIGMETRICS Performance Evaluation Review	2004	DBLP DOI BibTeX RDF
1	Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler	Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler	Scalable selective re-execution for EDGE architectures.	ASPLOS	2004	DBLP DOI BibTeX RDF	EDGE architectures, load-store dependence prediction, mis-speculation recovery, selective re-execution, selective replay, speculative dataflow machines
1	Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi	Coherence decoupling: making use of incoherence.	ASPLOS	2004	DBLP DOI BibTeX RDF	coherence decoupling, coherence misses, speculative cache lookup, false sharing
1	Changkyu Kim, Doug Burger, Stephen W. Keckler	Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore	Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Deependra Talla, Lizy Kurian John, Doug Burger	Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	bottlenecks in SIMD extensions, hardware address generation, low-overhead looping, superscalar general-purpose processors, performance evaluation, workload characterization, subword parallelism, Media processing, data reorganization
1	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static energy reduction techniques for microprocessor caches.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Kathryn S. McKinley, Charles C. Weems	Guided Region Prefetching: A Cooperative Hardware/Software Approach. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore	Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger	Microprocessor pipeline energy analysis.	ISLPED	2003	DBLP DOI BibTeX RDF	alpha 21264, over-provisioning, power, energy, speculation
1	Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler	Scalable Hardware Memory Disambiguation for High ILP Processors.	MICRO	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger	Universal Mechanisms for Data-Parallel Architectures.	MICRO	2003	DBLP DOI BibTeX RDF
1	Doug Burger	Designing Ultra-large Instruction Issue Windows.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger	Routed Inter-ALU Networks for ILP Scalability and Performance.	ICCD	2003	DBLP DOI BibTeX RDF
1	Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger	Exploiting Microarchitectural Redundancy For Defect Tolerance.	ICCD	2003	DBLP DOI BibTeX RDF
1	Doug Burger	Architectural versus physical solutions for on-chip communication challenges.	CODES+ISSS	2003	DBLP DOI BibTeX RDF
1	Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero	Errata on "Measuring Experimental Error in Microprocessor Simulation".	SIGARCH Computer Architecture News	2002	DBLP DOI BibTeX RDF
1	M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas	The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	instruction queue clock rate, Pipelining
1	Changkyu Kim, Doug Burger, Stephen W. Keckler	An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.	ASPLOS	2002	DBLP DOI BibTeX RDF
1	Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi	Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic.	DSN	2002	DBLP DOI BibTeX RDF
1	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Designing a Modern Memory Hierarchy with Hardware Prefetching.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design
1	Jaehyuk Huh, Doug Burger, Stephen W. Keckler	Exploring the Design Space of Future CMPs.	IEEE PACT	2001	DBLP DOI BibTeX RDF
1	Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler	A design space evaluation of grid processor architectures.	MICRO	2001	DBLP DOI BibTeX RDF
1	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Reducing DRAM Latencies with an Integrated Memory Hierarchy Design.	HPCA	2001	DBLP DOI BibTeX RDF
1	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static Energy Reduction Techniques for Microprocessor Caches.	ICCD	2001	DBLP BibTeX RDF
1	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger, Thomas R. Puzak	Filtering Superfluous Prefetches Using Density Vectors.	ICCD	2001	DBLP BibTeX RDF
1	Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger	Clock rate versus IPC: the end of the road for conventional microarchitectures.	ISCA	2000	DBLP DOI BibTeX RDF
1	Stefanos Kaxiras, Doug Burger, James R. Goodman	DataScalar: A memory-centric approach to computing.	Journal of Systems Architecture	1999	DBLP DOI BibTeX RDF
1	Doug Burger, James R. Goodman	Billion-Transistor Architectures - Guest Editors' Introduction.	IEEE Computer	1997	DBLP BibTeX RDF
1	Sarita V. Adve, Doug Burger, Rudolf Eigenmann, Alasdair Rawsthorne, Michael D. Smith, Catherine H. Gebotys, Mahmut T. Kandemir, David J. Lilja, Alok N. Choudhary, Jesse Zhixi Fang, Pen-Chung Yew	Changing Interaction of Compiler and Architecture.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Doug Burger, James R. Goodman, Gurindar S. Sohi	Memory Systems.	The Computer Science and Engineering Handbook	1997	DBLP BibTeX RDF
1	Doug Burger, Stefanos Kaxiras, James R. Goodman	DataScalar Architectures.	ISCA	1997	DBLP DOI BibTeX RDF
1	Alain Kägi, Doug Burger, James R. Goodman	Efficient Synchronization: Let Them Eat QOLB.	ISCA	1997	DBLP DOI BibTeX RDF
1	Doug Burger, Rahmat S. Hyder, Barton P. Miller, David A. Wood	Paging tradeoffs in distributed-shared-memory multiprocessors.	The Journal of Supercomputing	1996	DBLP DOI BibTeX RDF
1	Doug Burger	Memory Systems.	ACM Comput. Surv.	1996	DBLP DOI BibTeX RDF
1	Doug Burger, James R. Goodman, Alain Kägi	Memory Bandwidth Limitations of Future Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
1	Doug Burger, David A. Wood	Accuracy vs. performance in parallel simulation of interconnection networks. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	Wisconsin Wind Tunnel, cache-coherent shared-memory machines, network simulation models, high network loads, nonuniform traffic patterns, performance evaluation, performance, parallel computers, interconnection networks, parallel architectures, virtual machines, multiprocessor interconnection networks, accuracy, shared memory systems, parallel simulation, parallel applications, cache-coherence protocols, network contention
1	Alain Kägi, Nagi Aboulenein, Doug Burger, James R. Goodman	Techniques for Reducing Overheads of Shared-Memory Multiprocessing.	International Conference on Supercomputing	1995	DBLP DOI BibTeX RDF
1	Doug Burger, Rahmat S. Hyder, Barton P. Miller, David A. Wood	Paging tradeoffs in distributed-shared-memory multiprocessors.	SC	1994	DBLP BibTeX RDF

Publications of "Doug Burger" ( http://dblp.L3S.de/Authors/Doug_Burger )