| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Earl E. Swartzlander Jr., Hani Saleh |
FFT Implementation with Fused Floating-Point Operations.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan |
Keep it straight: teaching placement how to better handle designs with datapaths. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Inwook Kong, Earl E. Swartzlander Jr. |
A Goldschmidt Division Method With Faster Than Quadratic Convergence. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Waqas Akram, Earl E. Swartzlander Jr. |
Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr. |
Quantifying academic placer performance on custom designs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca (eds.) |
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 |
ASAP |
2011 |
DBLP BibTeX RDF |
|
| 1 | Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr. |
Design rules for Quantum-dot Cellular Automata. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr. |
Priority Tries for IP Address Lookup. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
binary trie, priority trie, range representation, Internet, router, IP address lookup |
| 1 | Ron S. Waters, Earl E. Swartzlander Jr. |
A Reduced Complexity Wallace Multiplier Reduction. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
High-speed multiplier, Wallace multiplier, Dadda multiplier |
| 1 | Terence K. Rodrigues, Earl E. Swartzlander Jr. |
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
angle rotation, sine computation, cosine computation, CORDIC algorithm |
| 1 | Inwook Kong, Earl E. Swartzlander Jr. |
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Waqas Akram, Earl E. Swartzlander Jr. |
A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr. |
QCA Systolic Matrix Multiplier. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham |
High speed recursion-free CORDIC architecture. |
SoCC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Heumpil Cho, Earl E. Swartzlander Jr. |
Adder and Multiplier Design in Quantum-Dot Cellular Automata. |
IEEE Trans. Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bassam Jamil Mohd, Earl E. Swartzlander Jr. |
A Power-Scalable Switch-Based Multi-processor FFT. |
ASAP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert J. Ascott, Earl E. Swartzlander Jr. |
JavaFlow - A Java dataflow machine. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr. |
ASIC evaluation of ECHO hash function. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngmoon Choi, Earl E. Swartzlander Jr. |
Speculative Carry Generation With Prefix Adder. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds |
Bridge Floating-Point Fused Multiply-Add Design. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Systolic FFT Processors: A Personal Perspective. |
Signal Processing Systems |
2008 |
DBLP DOI BibTeX RDF |
systolic systems, frequency domain adaptive digital filters, systolic FFT, fast fourier transforms |
| 1 | Robert T. Grisamore, Earl E. Swartzlander Jr. |
Negative Save Sign Extension for Multi-term Adders and Multipliers. |
Signal Processing Systems |
2008 |
DBLP DOI BibTeX RDF |
adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers |
| 1 | Eric Quinnell, Earl E. Swartzlander Jr. |
Floating-Point Computer Arithmetic. |
Wiley Encyclopedia of Computer Science and Engineering |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Fixed-Point Computer Arithmetic. |
Wiley Encyclopedia of Computer Science and Engineering |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijay K. Jain, Earl E. Swartzlander Jr. |
32 bit single cycle nonlinear VLSI cell for the ICA algorithm. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr. |
High performance IP lookup circuit using DDR SDRAM. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hani Saleh, Earl E. Swartzlander Jr. |
A floating-point fused dot-product unit. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
The Negative Two's Complement Number System. |
VLSI Signal Processing |
2007 |
DBLP DOI BibTeX RDF |
arithmetic and logic structures, computer arithmetic |
| 1 | Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. |
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Heumpil Cho, Earl E. Swartzlander Jr. |
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. |
IEEE Symposium on Computer Arithmetic |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. |
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Systolic FFT Processors: Past, Present and Future. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tung N. Pham, Earl E. Swartzlander Jr. |
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Moboluwaji O. Sanu, Earl E. Swartzlander Jr. |
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Three Dimensional System on Chip Technology, invited. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngmoon Choi, Earl E. Swartzlander Jr. |
Parallel Prefix Adder Design with Matrix Representation. |
IEEE Symposium on Computer Arithmetic |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
A Review of Large Parallel Counter Designs. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase |
Parallel Montgomery Multipliers. |
ASAP |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Ibrahim, Earl E. Swartzlander Jr. |
Guest Editorial. |
VLSI Signal Processing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayman M. El-Khashab, Earl E. Swartzlander Jr. |
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr. |
A self-testing method for the pipelined A/D converter. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr. |
Quadruple Time Redundancy Adders. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungwook Yu, Earl E. Swartzlander Jr. |
A scaled DCT architecture with the CORDIC algorithm. |
IEEE Transactions on Signal Processing |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr. |
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. |
VLSI Signal Processing |
2002 |
DBLP DOI BibTeX RDF |
3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, MAC, multiplier |
| 1 | Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall |
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang Yong Kang, Earl E. Swartzlander Jr. |
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungwook Yu, Earl E. Swartzlander Jr. |
A pipelined architecture for the multidimensional DFT. |
IEEE Transactions on Signal Processing |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungwook Yu, Earl E. Swartzlander Jr. |
DCT Implementation with Distributed Arithmetic. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
recursive DCT algorithm, Discrete Cosine Transform, distributed arithmetic |
| 1 | Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka |
A fast hybrid carry-lookahead/carry-select adder design. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
CMOS, domino logic, carry lookahead adder |
| 1 | K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte |
Analysis of Column Compression Multipliers. |
IEEE Symposium on Computer Arithmetic |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Tat Ngai, Earl E. Swartzlander Jr., Chen He |
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. (PDF / PS) |
DFT |
2001 |
DBLP DOI BibTeX RDF |
Alternating Logic, Fault Tolerance, TMR, Concurrent Error Correcting, Arithmetic Unit |
| 1 | Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr. |
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
Application specific processor architecture, Inverse Discrete Cosine Transform, serial-parallel processor, image compression, Discrete Cosine Transform, systolic array |
| 1 | W. Lynn Gallagher, Earl E. Swartzlander Jr. |
Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
fault-tolerant arithmetic, Newton-Raphson division, Goldschmidt division, time shared TMR, Division |
| 1 | Michael J. Schulte, Earl E. Swartzlander Jr. |
A Family of Variable-Precision Interval Arithmetic Processors. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
variable-precision arithmetic, computer arithmetic, accuracy, Processors, interval arithmetic, hardware designs, roundoff error |
| 1 | Jae-Hyuck Kwak, Jae Hun Choi, Earl E. Swartzlander Jr. |
High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. |
VLSI Signal Processing |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka |
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
3:2 counter, 4:2 compressor, 5:2 compressor, MAC, multiplier |
| 1 | Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri |
Fault-Tolerant High-Performance Cordic Processors. (PDF / PS) |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Francescomaria Marino, Earl E. Swartzlander Jr. |
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
multidimensional transforms, 2D DFT, 1D FFT, systolic VLSI architectures, Parallel processing |
| 1 | Gwangwoo Choe, Earl E. Swartzlander Jr. |
Bipolar merged arithmetic for wavelet architectures. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | W. Lynn Gallagher, Earl E. Swartzlander Jr. |
Power Consumption in Fast Dividers Using Time Shared TMR. (PDF / PS) |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Goldschmidt, time shared TMR, fault tolerant arithmetic, fault tolerance, division, TMR, Newton-Raphson |
| 1 | Vincenzo Piuri, Earl E. Swartzlander Jr. |
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. (PDF / PS) |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Time-Shared Modular Redundancy, FFT, Concurrent Error Detection, On-Line Testing, Concurrent Error Correction |
| 1 | Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr. |
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Low latency CORDIC architecture, Folded-transistor design, Area optimization |
| 1 | Earl E. Swartzlander Jr. |
Calculators. |
IEEE Annals of the History of Computing |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Calculators. |
IEEE Annals of the History of Computing |
1998 |
DBLP BibTeX RDF |
|
| 1 | Mary Jane Irwin, S. Y. Kung, Earl E. Swartzlander Jr. |
Editorial Message. |
VLSI Signal Processing |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
VLSI, MCM, and WSI: A Design Comparison. |
IEEE Design & Test of Computers |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Gwangwoo Choe, Earl E. Swartzlander Jr. |
Merged Arithmetic for Computing Wavelet Transforms. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | W. Lynn Gallagher, Earl E. Swartzlander Jr. |
Error-Correcting Goldschmidt Dividers Using Time Shared TMR. (PDF / PS) |
DFT |
1998 |
DBLP DOI BibTeX RDF |
Goldschmidt's algorithm, time shared TMR, TSTMR fault tolerance, fault tolerant arithmetic, division |
| 1 | Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr. |
Hybrid CORDIC Algorithms. |
IEEE Trans. Computers |
1997 |
DBLP DOI BibTeX RDF |
Givens transformation, planary rotator, CORDIC architecture, elementary function, CORDIC algorithm |
| 1 | Earl E. Swartzlander Jr. |
Calculators. |
IEEE Annals of the History of Computing |
1997 |
DBLP BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
High-Speed Computer Arithmetic. |
The Computer Science and Engineering Handbook |
1997 |
DBLP BibTeX RDF |
|
| 1 | Edwin de Angel, Earl E. Swartzlander Jr. |
Survey of low power techniques for ROMs. |
ISLPED |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr. |
Realization of a nonlinear digital filter on a DSP array processor. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing |
| 1 | Thomas K. Callaway, Earl E. Swartzlander Jr. |
Power-Delay Characteristics of CMOS Multipliers. |
IEEE Symposium on Computer Arithmetic |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | W. Lynn Gallagher, Earl E. Swartzlander Jr. |
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. (PDF / PS) |
DFT |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Schulte, Earl E. Swartzlander Jr. |
Variable-precision, interval arithmetic coprocessors. |
Reliable Computing |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Calculators. |
IEEE Annals of the History of Computing |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Calculators. (PDF / PS) |
IEEE Annals of the History of Computing |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr. |
A new design for a lookahead carry generator. |
VLSI Signal Processing |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr. |
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors |
| 1 | K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr. |
Parallel reduced area multipliers. |
VLSI Signal Processing |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Schulte, Earl E. Swartzlander Jr. |
A Processor for Staggered Interval Arithmetic. |
ASAP |
1995 |
DBLP DOI BibTeX RDF |
computer arithmetic, hardware, processor, Interval arithmetic, precision, application specific, numerical computations |
| 1 | Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri |
Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. |
ASAP |
1995 |
DBLP DOI BibTeX RDF |
neural networks, fault tolerance, time redundancy |
| 1 | Shaoyun Wang, Earl E. Swartzlander Jr. |
Merged CORDIC Algorithm. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr. |
Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr. |
Fault-Tolerant Neural Architectures: The Use of Rotated Operands. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr. |
Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. |
IEEE Symposium on Computer Arithmetic |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Schulte, Earl E. Swartzlander Jr. |
Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. |
IEEE Symposium on Computer Arithmetic |
1995 |
DBLP DOI BibTeX RDF |
arithmetic algorithms, computer arithmetic, hardware, Interval arithmetic, precision, coprocessor, numerical computations |
| 1 | Hyesook Lim, Earl E. Swartzlander Jr. |
An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . (PDF / PS) |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
prime-factor decomposition, index mappings, VLSI, discrete cosine transforms, discrete cosine transform, systolic arrays, systolic array, VLSI implementation, array signal processing |
| 1 | Michael J. Schulte, Earl E. Swartzlander Jr. |
A coprocessor for accurate and reliable numerical computations. (PDF / PS) |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
reliable numerical computations, direct hardware support, logic design, digital arithmetic, interval arithmetic, hardware design, coprocessors, coprocessor, numerical computations |
| 1 | Michael J. Schulte, J. Omar, Earl E. Swartzlander Jr. |
Optimal initial approximations for the Newton-Raphson division algorithm. |
Computing |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Schulte, Earl E. Swartzlander Jr. |
Hardware Designs for Exactly Rounded Elemantary Functions. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
Chebyshev approximation, summing circuits, exactly rounded elementary functions, multi-operand adder, Chebyshev series approximation, single-precision floating point numbers, chip area, 1.0-micron CMOS technology, computational delay, exact rounding, argument reduction, computer arithmetic, digital arithmetic, polynomials, CMOS integrated circuits, multiplying circuits, square-root, hardware designs, reciprocal, approximation theory, polynomial approximation, special-purpose hardware, parallel multiplier, 1 micron |
| 1 | Earl E. Swartzlander Jr. |
Editorial. |
VLSI Signal Processing |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert F. Jones, Earl E. Swartzlander Jr. |
Parallel counter implementation. |
VLSI Signal Processing |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Ben C. Drerup, Earl E. Swartzlander Jr. |
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. |
VLSI Signal Processing |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas A. Ziaja, Earl E. Swartzlander Jr. |
Boundary scan in board manufacturing. |
J. Electronic Testing |
1994 |
DBLP DOI BibTeX RDF |
Board and system test, boundary scan description language, design-for-test, boundary scan |
| 1 | Thomas L. Casavant, Chi-Yuan Chin, Wen-Tsuen Chen, Kang G. Shin, Earl E. Swartzlander Jr., Joseph E. Urban |
What Types of Research Papers Should We Be Writing? |
ICPADS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Earl E. Swartzlander Jr. |
Heterogeneous Parallel Computing. |
ICPADS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Yuang-Ming Hsu, Earl E. Swartzlander Jr. |
Sorting Networks with Built-In Error Correction. |
ICPADS |
1994 |
DBLP BibTeX RDF |
|
| 1 | José Duato, C. T. Howard Ho, Ferng-Ching Lin, Lionel M. Ni, Earl E. Swartzlander Jr. |
Is It Possible to Fairly Compare Interconnection Networks?. |
ICPADS |
1994 |
DBLP BibTeX RDF |
|
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