Search results for "Eby G. Friedman"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny	Multi-aggressor capacitive and inductive coupling noise modeling and mitigation.	Microelectronics Journal	2012	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman	Utilizing interdependent timing constraints to enhance robustness in synchronous circuits.	Microelectronics Journal	2012	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	Efficient algorithms for fast IR drop analysis exploiting locality.	Integration	2012	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman, Simon Tarn, Sally Pinzon, Bruce McDermott	An area efficient on-chip hybrid voltage regulator.	ISQED	2012	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Link breaking methodology: mitigating noise within power networks.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Jinhui Wang, Ioannis Savidis, Eby G. Friedman	Thermal analysis of oxide-confined VCSEL arrays.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman	Clock Distribution Networks in 3-D Integrated Systems.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Selçuk Köse, Emre Salman, Eby G. Friedman	Shielding Methodologies in the Presence of Power/Ground Noise.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Multi-Layer Interdigitated Power Distribution Networks.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	Linear and Switch-Mode Conversion in 3-D Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	Effective Resistance of a Two Layer Mesh.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	Distributed power network co-design with on-chip power supplies and decoupling capacitors.	SLIP	2011	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	Fast algorithms for IR voltage drop analysis exploiting locality.	DAC	2011	DBLP DOI BibTeX RDF
1	Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman	Clock distribution models of 3-D integrated systems.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman	Memristor-based IMPLY logic design procedure.	ICCD	2011	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Resource Based Optimization for Simultaneous Shield and Repeater Insertion.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore	An intra-chip free-space optical interconnect.	ISCA	2010	DBLP DOI BibTeX RDF	free-space optical interconnect, intra-chip, 3d
1	Emre Salman, Eby G. Friedman	Methodology to achieve higher tolerance to delay variations in synchronous circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	delay uncertainty, environmental variation, robust circuit, process variation, tolerance
1	Selçuk Köse, Eby G. Friedman	On-chip point-of-load voltage regulator for distributed power supplies.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	dc-dc voltage regulation, on-chip voltage regulator, power delivery, active filter
1	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
1	Renatas Jakushokas, Eby G. Friedman	Line width optimization for interdigitated power/ground networks.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	interdigitated structure, optimal line width, power/ground network, power network
1	Renatas Jakushokas, Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin, Cynthia L. Recker	Compact substrate models for efficient noise coupling and signal isolation analysis.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Methodology for multi-layer interdigitated power and ground network design.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	An area efficient fully monolithic hybrid voltage regulator.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Globally integrated power and clock distribution network.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	Fast algorithms for power grid analysis based on effective resistance.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson	Efficiency optimization of integrated DC-DC buck converters.	ICECS	2010	DBLP DOI BibTeX RDF
1	Selçuk Köse, Eby G. Friedman	Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors.	SoCC	2010	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Inductance Model of Interdigitated Power and Ground Distribution Networks.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	On-chip DC-DC converters for three-dimensional ICs.	ISQED	2009	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Simultaneous shield and repeater insertion.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay, interconnects, noise, power, area
1	Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Contact merging algorithm for efficient substrate noise analysis in large scale circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	noise coupling, substrate modeling, signal integrity, mixed-signal circuits, substrate noise, noise analysis
1	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
1	Eby G. Friedman	Design challenges in high performance three-dimensional circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	VLSI, NOC, 3-D, clock distribution
1	Renatas Jakushokas, Eby G. Friedman	Minimizing Noise Via Shield and Repeater Insertion.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Selçuk Köse, Emre Salman, Eby G. Friedman	Shielding Methodologies in the Presence of Power/Ground Noise.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman	Effective Radii of On-Chip Decoupling Capacitors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny	On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	Timing-driven via placement heuristics for three-dimensional ICs.	Integration	2008	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.	ISQED	2008	DBLP DOI BibTeX RDF	signal integrity, mixed-signal circuits, Substrate coupling
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
1	Guoqing Chen, Eby G. Friedman	Transient simulation of on-chip transmission lines via exact pole extraction.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Input port reduction for efficient substrate extraction in large scale IC's.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Equivalent rise time for resonance in power/ground noise estimation.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Ioannis Savidis, Eby G. Friedman	Electrical modeling and characterization of 3-D vias.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman	Nanoscale on-chip decoupling capacitors.	SoCC	2008	DBLP DOI BibTeX RDF
1	Selçuk Köse, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman	Pseudo-random clocking to enhance signal integrity.	SoCC	2008	DBLP DOI BibTeX RDF
1	Alexander Lavzin, Mücahit Kozak, Eby G. Friedman	A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators.	SoCC	2008	DBLP DOI BibTeX RDF
1	Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman	Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	Design Methodology for Global Resonant H-Tree Clock Distribution Networks.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	3-D Topologies for Networks-on-Chip.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman	Predictions of CMOS compatible on-chip optical interconnect.	Integration	2007	DBLP DOI BibTeX RDF
1	Magdy A. El-Moursy, Eby G. Friedman	Wire shaping of RLC interconnects.	Integration	2007	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Substrate Noise Reduction Based On Noise Aware Cell Design.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	Quasi-Resonant Interconnects: A Low Power Design Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin	Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs.	ICCAD	2007	DBLP DOI BibTeX RDF	power distribution grids, power noise, decoupling capacitors, power distribution systems
1	Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman	Sizing CMOS inverters with Miller Effect and Threshold voltage Variations.	Journal of Circuits, Systems, and Computers	2006	DBLP DOI BibTeX RDF
1	Junmou Zhang, Eby G. Friedman	Crosstalk modeling for coupled RLC interconnects with application to shield insertion.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman	Decoupling capacitors for multi-voltage power distribution systems.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar	Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times.	ISQED	2006	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	Sensitivity evaluation of global resonant H-tree clock distribution networks.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	H-tree sector, on-chip inductors and capacitors, sensitivity, resonance, clock distribution networks
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu	Maximum effective distance of on-chip decoupling capacitors in power distribution grids.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power distribution grids, decoupling capacitors, power distribution systems
1	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire tapering for minimum power dissipation in RLC interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman	On-die decoupling capacitance: frequency domain analysis of activity radius.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jonathan Rosenfeld, Eby G. Friedman	Design methodology for global resonant H-tree clock distribution networks.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Effective capacitance of RLC loads for estimating short-circuit power.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	Via placement for minimum interconnect delay in three-dimensional (3D) circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra	Monolithic voltage conversion in low-voltage CMOS technologies.	Microelectronics Journal	2005	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	An RLC interconnect model based on fourier analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Magdy A. El-Moursy, Eby G. Friedman	Exponentially tapered H-tree clock distribution networks.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman	Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems.	ISQED	2005	DBLP DOI BibTeX RDF
1	Vasilis F. Pavlidis, Eby G. Friedman	Interconnect delay minimization through interlayer via placement in 3-D ICs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	RC interconnects, elmore delay, 3-D ICs
1	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny	On-chip power distribution grids with multiple supply voltages for high performance integrated circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple power supply voltages, power distribution grids, decoupling capacitors, power distribution systems
1	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Predictions of CMOS compatible on-chip optical interconnect.	SLIP	2005	DBLP DOI BibTeX RDF	CMOS compatible, on-chip, optical interconnect, trends
1	Guoqing Chen, Eby G. Friedman	A Fourier series-based RLC interconnect model for periodic signals.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra	Cascode buffer for monolithic voltage conversion operating at high input supply voltages.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Low power repeaters driving RLC interconnects with delay and bandwidth constraints.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernández, Eby G. Friedman	Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Electrical and optical on-chip interconnects in scaled microprocessors.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Mikhail Popovich, Eby G. Friedman	Noise coupling in multi-voltage power distribution systems with decoupling capacitors.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Andrey V. Mezhiba, Eby G. Friedman	Impedance characteristics of power distribution grids in nanoscale integrated circuits.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Magdy A. El-Moursy, Eby G. Friedman	Power characteristics of inductive interconnect.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Andrey V. Mezhiba, Eby G. Friedman	Scaling trends of on-chip power distribution noise.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Volkan Kursun, Eby G. Friedman	Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman	Substrate coupling in digital circuits in mixed-signal smart-power systems.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman	Complex +/-1 Multiplier Based on Signed-Binary Transformations.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	PN code scrambler, complex ±1 multiplier, signed-binary number representation, VLSI, CDMA, redundant arithmetic
1	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters .	Integration	2004	DBLP DOI BibTeX RDF
1	Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman	High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.	ISQED	2004	DBLP DOI BibTeX RDF

Publications of "Eby G. Friedman" ( http://dblp.L3S.de/Authors/Eby_G._Friedman )