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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4 occurrences of 4 keywords
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Results
Found 8 publication records. Showing 8 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin |
CAFES: A framework for intrachip application modeling and communication architecture design.  |
J. Parallel Distrib. Comput.  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
Arbitration and routing impact on NoC design. |
International Symposium on Rapid System Prototyping |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
Comparison of network-on-chip mapping algorithms targeting low energy consumption. |
IET Computers & Digital Techniques |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya |
Integrating Abstract NoC Models within MPSoC Design. |
IEEE International Workshop on Rapid System Prototyping |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno |
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture |
CoRR |
2007 |
DBLP BibTeX RDF |
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| 1 | César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
Evaluation of Algorithms for Low Energy Mapping onto NoCs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno |
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara |
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. |
SBCCI |
2003 |
DBLP DOI BibTeX RDF |
transaction level, VHDL, SystemC, System modeling, register transfer level |
Displaying result #1 - #8 of 8 (100 per page; Change: )
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