Search results for "Edward David Moreno Ordonez"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Cesar Giacomini Penteado, Sergio Takeo Kofuji, Edward D. Moreno	A Flexible and Parameterized Architecture for Multicore Microcontroller.	JCP	2011	DBLP DOI BibTeX RDF
1	Marina L. Gavrilova, Chih Jeng Kenneth Tan, Edward D. Moreno (eds.)	Transactions on Computational Science X - Special Issue on Security in Computing, Part I	Transactions on Computational Science	2010	DBLP DOI BibTeX RDF
1	Fábio Dacêncio Pereira, Edward D. Moreno	Performance Issues on Integration of Security Services.	Transactions on Computational Science	2010	DBLP DOI BibTeX RDF
1	Marina L. Gavrilova, Chih Jeng Kenneth Tan, Edward D. Moreno (eds.)	Transactions on Computational Science XI - Special Issue on Security in Computing, Part II	Transactions on Computational Science	2010	DBLP DOI BibTeX RDF
1	Marina L. Gavrilova, Chih Jeng Kenneth Tan, Edward D. Moreno (eds.)	Transactions on Computational Science IV, Special Issue on Security in Computing	Transactions on Computational Science	2009	DBLP DOI BibTeX RDF
1	Fábio Dacêncio Pereira, Edward David Moreno Ordonez	A Hardware Architecture for Integrated-Security Services.	Transactions on Computational Science	2009	DBLP DOI BibTeX RDF	Integrated Security Services, FPGA Performance and System-on-Chip, Embedded System
1	Alexandre Ponce de Oliveira, Edward D. Moreno	Impact of the DES and AES Algorithms on PERS (A Specific Processor for Sensor Networks).	ICSNC	2007	DBLP DOI BibTeX RDF
1	Kalinka Regina Lucas Jaquie Castelo Branco, Edward David Moreno Ordonez	Load Indices on Heterogeneous Systems- Past, Present and Future.	JCIT	2007	DBLP BibTeX RDF
1	Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte	A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Edward David Moreno Ordonez	Hash Join Algorithms on SMPs Clusters: Effects of Netcaches on Its Scalability and Performance.	J. Inf. Sci. Eng.	2002	DBLP BibTeX RDF
1	Edward D. Moreno, Sergio Takeo Kofuji	Improvements on bus technology will affect the benefits of remote caches in CC-NUMA architectures.	Computers and Their Applications	1998	DBLP BibTeX RDF
1	Edward D. Moreno, Sergio Takeo Kofuji, Marcelo H. Cintra	Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets.	Euro-Par	1997	DBLP DOI BibTeX RDF
1	Edward D. Moreno, Sergio Takeo Kofuji, Michael Stumm, Tarek S. Abdelrahman	Tuning Shared Network Cache Size vs. Second-Level Cache Size in Clusters-Based Multiprocessors.	PaCT	1997	DBLP DOI BibTeX RDF
1	Edward D. Moreno, Sergio Takeo Kofuji	Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results.	ISPAN	1997	DBLP DOI BibTeX RDF	shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness
1	Edward David Moreno Ordonez, Sergio Takeo Kofuji	Performance evaluation of the fixed sequential prefetching on a bus-based multiprocessor: preliminary results.	ISPAN	1996	DBLP DOI BibTeX RDF	fixed sequential prefetching, bus-based multiprocessor, sequential prefetching, OBL policy, performance evaluation, performance evaluation, Petri nets, Petri nets, shared memory systems, shared memory systems, cache storage, data prefetching

Publications of Edward David Moreno Ordonez Edward D. Moreno ( http://dblp.L3S.de/Authors/Edward_David_Moreno_Ordonez )