Search results for "Edward J. McCluskey"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ahmad A. Al-Yamani, Edward J. McCluskey	Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns.	J. Electronic Testing	2010	DBLP DOI BibTeX RDF
1	Jaekwang Lee, Edward J. McCluskey	Failing Frequency Signature Analysis.	ITC	2008	DBLP DOI BibTeX RDF
1	Intaik Park, Edward J. McCluskey	Launch-on-Shift-Capture Transition Tests.	ITC	2008	DBLP DOI BibTeX RDF
1	Jaekwang Lee, Intaik Park, Edward J. McCluskey	Error Sequence Analysis.	VTS	2008	DBLP DOI BibTeX RDF
1	François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh	How Many Test Patterns are Useless?	VTS	2008	DBLP DOI BibTeX RDF	Test Patterns, Test Economics, Truncation
1	Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey	Inconsistent Fail due to Limited Tester Timing Accuracy.	VTS	2008	DBLP DOI BibTeX RDF	inconsistent fail, tester timing accuracy, tester EPA, delay test, inconsistency
1	Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey	California scan architecture for high quality and low power testing.	ITC	2007	DBLP DOI BibTeX RDF
1	Kyoung Youn Cho, Edward J. McCluskey	Test Set Reordering Using the Gate Exhaustive Test Metric.	VTS	2007	DBLP DOI BibTeX RDF
1	François-Fabien Ferhani, Edward J. McCluskey	Classifying Bad Chips and Ordering Test Sets.	ITC	2006	DBLP DOI BibTeX RDF
1	Erik Chmelar, Edward J. McCluskey	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Edward J. McCluskey	Test chip experimental results on high-level structural test.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test experiment, Structural test, VLSI test, complex gates
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Edward J. McCluskey	BIST-Guided ATPG.	ISQED	2005	DBLP DOI BibTeX RDF
1	Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey	Gate exhaustive testing.	ITC	2005	DBLP DOI BibTeX RDF
1	Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey	Effective TARO Pattern Generation.	VTS	2005	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Efficient Design Diversity Estimation for Combinational Circuits.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	common-mode failures, reliability, fault-tolerant computing, dependability, Error detection, design diversity
1	Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey	Reconfigurable Architecture for Autonomous Self-Repair.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra	Speed Clustering of Integrated Circuits.	ITC	2004	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure	A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs.	VTS	2004	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger	Delay Defect Screening using Process Monitor Structures.	VTS	2004	DBLP DOI BibTeX RDF
1	Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra	ELF-Murphy Data on Defects and Test Sets.	VTS	2004	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Edward J. McCluskey	Seed encoding with LFSRs and cellular automata.	DAC	2003	DBLP DOI BibTeX RDF	built-in self test, VLSI Test, reseeding
1	Ahmad A. Al-Yamani, Edward J. McCluskey	Built-In Reseeding for Serial Bist.	VTS	2003	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Bist Reseeding with very few Seeds.	VTS	2003	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	A Design Diversity Metric and Analysis of Redundant Systems.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	common-mode failures, fault-tolerant computing, dependability, Error detection, design diversity
1	Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey	ED4I: Error Detection by Diverse Data and Duplicated Instructions.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Software implemented hardware fault tolerance (SIHFT), low cost fault tolerance, data diversity, duplicated instructions, concurrent error detection
1	Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey	Fault Grading FPGA Interconnect Test Configurations.	ITC	2002	DBLP DOI BibTeX RDF
1	Chao-Wen Tseng, James Li, Edward J. McCluskey	Experimental Results for Slow-Speed Testing.	VTS	2002	DBLP DOI BibTeX RDF
1	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of Sequence-Dependent Chips.	VTS	2002	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey, Samy Makar	Design for Testability and Testing of IEEE 1149.1 Tap Controller.	VTS	2002	DBLP DOI BibTeX RDF
1	Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers	Debating the Future of Burn-In. (PDF / PS)	VTS	2002	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Testing Digital Circuits with Constraints. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Dependable Reconfigurable Computing Design Diversity and Self Repair. (PDF / PS)	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	Bit-fixing in pseudorandom sequences for scan BIST.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Diversity Techniques for Concurrent Error Detection. (PDF / PS)	ISQED	2001	DBLP DOI BibTeX RDF
1	Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey	Testing for resistive opens and stuck opens.	ITC	2001	DBLP DOI BibTeX RDF
1	Chao-Wen Tseng, Edward J. McCluskey	Multiple-output propagation transition fault test.	ITC	2001	DBLP DOI BibTeX RDF
1	Shu-Yi Yu, Edward J. McCluskey	On-line testing and recovery in TMR systems for real-time applications.	ITC	2001	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Techniques for Estimation of Design Diversity for Combinational Logic Circuits.	DSN	2001	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Design of Redundant Systems Protected Against Common-Mode Failures.	VTS	2001	DBLP DOI BibTeX RDF
1	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of Tunneling Opens.	VTS	2001	DBLP DOI BibTeX RDF
1	Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh	MINVDD Testing for Weak CMOS ICs.	VTS	2001	DBLP DOI BibTeX RDF
1	Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson	An Evaluation of Pseudo Random Testing for Detecting Real Defects.	VTS	2001	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Design Diversity for Concurrent Error Detection in Sequential Logic Circuts.	VTS	2001	DBLP DOI BibTeX RDF
1	Wei-Je Huang, Edward J. McCluskey	A memory coherence technique for online transient error recovery of FPGA configurations.	FPGA	2001	DBLP DOI BibTeX RDF	fault tolerance, FPGA, error recovery, memory coherence
1	Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey	Fast Run-Time Fault Location in Dependable FPGA-Based Applications. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Run-time fault location, Field-Programmable Gate Array (FPGA), concurrent error detection, on-line testing
1	Shu-Yi Yu, Edward J. McCluskey	Permanent Fault Repair for FPGAs with Limited Redundant Area. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Permanent Fault Repair, Adaptive Computing System, Reconfigurable Computing System, Fault Tolerance, FPGA, Recovery
1	Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey	Performance Evaluation of Checksum-Based ABFT. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	ABFT, Computation capacity, Performace evaluation, Data processing recovery schemes, Algorithm-based fault tolerance, Checksum, Early detection
1	Nahmsuk Oh, Edward J. McCluskey	Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	software error detection, low power technique, low energy technique, procedure duplication and instruction duplication, Fault tolerance
1	Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey	Efficient Multiplexer Synthesis Techniques.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey	Dependable Computing and Online Testing in Adaptive and Configurable Systems.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Wei-Je Huang, Edward J. McCluskey	Transient errors and rollback recovery in LZ compression.	PRDC	2000	DBLP DOI BibTeX RDF	LZ compression, Lempel-Ziv compression, compressed codewords, rollback error recovery schemes, data integrity, data integrity, fault tolerant computing, data compression, error detection, system recovery, transient faults, rollback recovery, compression ratio, lossless data compression, transient errors, data reconstruction, hardware redundancy
1	Chien-Mo James Li, Edward J. McCluskey	Testing for tunneling opens.	ITC	2000	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Combinational logic synthesis for diversity in duplex systems.	ITC	2000	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Edward J. McCluskey	Which concurrent error detection scheme to choose ?	ITC	2000	DBLP DOI BibTeX RDF
1	Edward J. McCluskey, Chao-Wen Tseng	Stuck-fault tests vs. actual defects.	ITC	2000	DBLP DOI BibTeX RDF
1	Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey	An ACS Robotic Control Algorithm with Fault Tolerant Capabilities.	FCCM	2000	DBLP DOI BibTeX RDF
1	Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey	A Reliable LZ Data Compressor on Reconfigurable Coprocessors.	FCCM	2000	DBLP DOI BibTeX RDF
1	Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu	Cold Delay Defect Screening.	VTS	2000	DBLP DOI BibTeX RDF	Manufacturing quality, Reliability, Delay Testing
1	Subhasish Mitra, Edward J. McCluskey	Word Voter: A New Voter Design for Triple Modular Redundant Systems.	VTS	2000	DBLP DOI BibTeX RDF	Word-Voter, TMR-Simplex, data integrity, Triple Modular redundancy (TMR), Voter
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Fault Escapes in Duplex Systems.	VTS	2000	DBLP DOI BibTeX RDF	Duplex systems, Common-Mode Failures (CMFs), Test points, User-programmable logic, Data Integrity, Availability, Diversity
1	Nur A. Touba, Edward J. McCluskey	RP-SYN: synthesis of random pattern testable circuits with test point insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey	An output encoding problem and a solution technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	A design diversity metric and reliability analysis for redundant systems.	ITC	1999	DBLP DOI BibTeX RDF
1	Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey	Finite state machine synthesis with concurrent error detection.	ITC	1999	DBLP DOI BibTeX RDF
1	Philip P. Shirvani, Edward J. McCluskey	PADded Cache: A New Fault-Tolerance Technique for Cache Memories.	VTS	1999	DBLP DOI BibTeX RDF
1	Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey	Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.	ITC	1998	DBLP DOI BibTeX RDF
1	Jonathan T.-Y. Chang, Edward J. McCluskey	Detecting resistive shorts for CMOS domino circuits.	ITC	1998	DBLP DOI BibTeX RDF
1	Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey	Experimental Results for IDDQ and VLV Testing. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Nirmal R. Saxena, Edward J. McCluskey	Parallel Signatur Analysis Design with Bounds on Aliasing.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	aliasing probability bounds, parallel signature designs, multiple input signature registers (MISR), linear feedback shift registers, random testing, Signature analysis
1	Nur A. Touba, Edward J. McCluskey	Logic synthesis of multilevel circuits with concurrent error detection.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey	Scan Synthesis for One-Hot Signals.	ITC	1997	DBLP DOI BibTeX RDF
1	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
1	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
1	Robert B. Norwood, Edward J. McCluskey	High-Level Synthesis for Orthogonal Sca.	VTS	1997	DBLP DOI BibTeX RDF
1	Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey	An output encoding problem and a solution technique.	ICCAD	1997	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	Pseudo-Random Pattern Testing of Bridging Faults.	ICCD	1997	DBLP BibTeX RDF
1	Nirmal R. Saxena, Edward J. McCluskey	Counting Two-State Transition-Tour Sequences.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Transition-tours, sequential machine testing, testable synthesis, checking experiments, Fibonacci numbers
1	Robert B. Norwood, Edward J. McCluskey	Orthogonal Scan: Low-Overhead Scan for Data Paths.	ITC	1996	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	Altering a Pseudo-Random Bit Sequence for Scan-Based BIST.	ITC	1996	DBLP DOI BibTeX RDF
1	Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell	Analysis and Detection of Timing Failures in an Experimental Test Chip.	ITC	1996	DBLP DOI BibTeX RDF
1	Jonathan T.-Y. Chang, Edward J. McCluskey	Detecting Delay Flaws by Very-Low-Voltage Testing.	ITC	1996	DBLP DOI BibTeX RDF
1	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
1	Nur A. Touba, Edward J. McCluskey	Test point insertion based on path tracing.	VTS	1996	DBLP DOI BibTeX RDF	probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test
1	Nur A. Touba, Edward J. McCluskey	Applying two-pattern tests using scan-mapping.	VTS	1996	DBLP DOI BibTeX RDF	scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
1	Jonathan T.-Y. Chang, Edward J. McCluskey	Quantitative analysis of very-low-voltage testing.	VTS	1996	DBLP DOI BibTeX RDF	very-low-voltage testing, static CMOS chips, supply voltage, rated conditions, early-life failures, test conditions, test speed, VLSI, VLSI, integrated circuit testing, CMOS integrated circuits, failure analysis, quantitative analysis, threshold voltage, integrated circuit noise
1	Kiyoshi Furuya, Seiji Seki, Edward J. McCluskey	Design of Autonomous TPG Circuits for Use in Two-Pattern Testing.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey	Floating Point Fault Tolerance with Backward Error Assertions.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
1	Siyad C. Ma, Edward J. McCluskey	Open faults in BiCMOS gates.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Siyad C. Ma, Piero Franco, Edward J. McCluskey	An Experimental Chip to Evaluate Test Techniques: Experiment Results.	ITC	1995	DBLP DOI BibTeX RDF
1	Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey	An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design.	ITC	1995	DBLP DOI BibTeX RDF
1	Samy Makar, Edward J. McCluskey	Functional Tests for Scan Chain Latches.	ITC	1995	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST.	ITC	1995	DBLP DOI BibTeX RDF
1	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
1	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
1	Nur A. Touba, Edward J. McCluskey	Transformed pseudo-random patterns for BIST.	VTS	1995	DBLP DOI BibTeX RDF	pseudorandom patterns transformation, onchip test pattern generation, mapping logic, on-chip TPG, logic testing, built-in self test, integrated circuit testing, logic design, BIST, combinational circuits, automatic testing, combinational logic
1	Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao	An apparatus for pseudo-deterministic testing.	VTS	1995	DBLP DOI BibTeX RDF	pseudo-deterministic testing, deterministic patterns, at-speed BIST, arbitrary length shift register, care bits, tap configurations, test segments, don't care bits, random pattern resistant faults, interconnected logic blocks, logic testing, built-in self test, integrated circuit testing, LFSR, shift registers, computational efficiency, test vector, pseudo-random sequences
1	Nirmal R. Saxena, Edward J. McCluskey	Linear Complexity Assertions for Sorting.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	linear complexity assertions, sorting programs, programs correctness checking, order assertion, permutation assertion, sorted data, descending order, ascending order, output data, order-sum assertion, partition theory, watchdog checker, program verification, sorting, error detection, programming theory, program debugging, execution time, program diagnostics, error checking, program execution, partition functions, input data
1	Nur A. Touba, Edward J. McCluskey	Automated Logic Synthesis of Random-Pattern-Testable Circuits.	ITC	1994	DBLP DOI BibTeX RDF

Publications of "Edward J. McCluskey" ( http://dblp.L3S.de/Authors/Edward_J._McCluskey )