Search results for "Einar J. Aas"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Design of embedded TCAM based longest prefix match search engine.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef	A programmable BIST with macro and micro codes for embedded SRAMs.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	An Enhanced Path Delay Fault Simulator for Combinational Circuits.	DSD	2011	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Experiments with ABIST test methodology applied to path delay fault testing.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Path-Delay Fault Testing in Embedded Content Addressable Memories.	DSD	2010	DBLP DOI BibTeX RDF
1	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Design of novel CAM core cell structures for an efficient implementation of low power BCAM system.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	binary content addressable memory (bcam), core cell, match line scheme, low power
1	Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas	Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Memory architecture exploration, High level synthesis, Memory optimization, Multi-media, Code transformation
1	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
1	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas	Probabilistic gate-level power estimation using a novel waveform set method.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	probabilistic power estimation, probability waveform, transition density, combinational logic, gate-level
1	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.	DFT	2006	DBLP DOI BibTeX RDF
1	Oystein Gjermundnes, Einar J. Aas	Remote Path Delay Fault Simulation.	DSD	2005	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Storage requirement estimation for optimized design of data intensive applications.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	data optimization, memory architecture exploration, high-level synthesis, code transformation, Size estimation
1	Øyvind Strøm, Kjetil Svarstad, Einar J. Aas	On the Utilization of Java Technology in Embedded Systems.	Design Autom. for Emb. Sys.	2003	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Data dependency size estimation for use in memory optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Øyvind Strøm, Einar J. Aas	An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code.	DSD	2001	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications.	DAC	2001	DBLP DOI BibTeX RDF
1	Einar J. Aas	Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences.	ISQED	2000	DBLP DOI BibTeX RDF	design efficiency, metrics, design experiments, design quality
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering.	ICCAD	2000	DBLP BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Storage requirement estimation for data intensive applications with partially fixed execution ordering.	CODES	2000	DBLP DOI BibTeX RDF
1	Øyvind Strøm, Audun Klauseie, Einar J. Aas	A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Einar J. Aas, Tore Steen, Karl Klingsheim	Quantifying Design Quality Through Design Experiments.	IEEE Design & Test of Computers	1994	DBLP DOI BibTeX RDF
1	Ayman M. Wahba, Einar J. Aas	Verification and Diagnosis of Digital Systems by Termary Reasoning.	CHARME	1993	DBLP DOI BibTeX RDF
1	Bjørg Reppen, Einar J. Aas	Combined probabilistic testability calculation and compact test generation for PLAs.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
1	Ove Brynestad, Einar J. Aas, Anne E. Vallestad	State transition graph analysis as a key to BIST fault coverage.	ITC	1990	DBLP DOI BibTeX RDF
1	Hedayat Markus Bayegan, Einar J. Aas	An integrated system for interactive editing of schematics, logic simulation and PCB layout design.	DAC	1978	DBLP BibTeX RDF
1	P. A. Arneberg, Einar J. Aas	Design automation in norway.	DAC	1975	DBLP BibTeX RDF

Publications of "Einar J. Aas" ( http://dblp.L3S.de/Authors/Einar_J._Aas )