Search results for "Electronic Design Automation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Andrew DeOrio, Valeria Bertacco	Electronic design automation for social networks.	DAC	2010	DBLP DOI BibTeX RDF	EDA algorithms, verification, social networks
2	Giovanni Stracquadanio, Concetta Drago, Vittorio Romano, Giuseppe Nicosia	Multi-objective optimization of doping profile in semiconductor design.	GECCO	2010	DBLP DOI BibTeX RDF	semiconductor design, multi-objective optimization, electronic design automation
2	Mi Zhang 0002, Guang Hu, Shi-liang Tu, ZhiLei Chai	Dynamic Electronic Design Automation concept, benefit and framework.	Int. Conf. Interaction Sciences	2009	DBLP DOI BibTeX RDF	dynamic EDA, system-level design language, reflection, dynamicity, Python, introspection
2	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Safe Delay Optimization for Physical Synthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	safe delay optimization, SafeResynth, safe resynthesis technique, immediately-measurable delay improvement, circuit timing, route length, physical synthesis, electronic design automation, route congestion, circuit delay
2	Debasri Saha, Susmita Sur-Kolay	Fast Robust Intellectual Property Protection for VLSI Physical Design.	ICIT	2007	DBLP DOI BibTeX RDF	fingerprint- ing, VLSI physical design, watermarking, Intellectual property, electronic design automation
2	Sachin S. Sapatnekar, Leon Stok	DAC Highlights.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	semiconductor industry, DAC, electronic design automation, automotive electronics, Design Automation Conference
2	Xuewen Xia, Yuanxiang Li, Weiqin Ying, Lei Chen	Automated Design Approach for Analog Circuit Using Genetic Algorithm.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	Evolutionary algorithms, Evolving hardware, Electronic Design Automation
2	Kartikeya Mayaram	CEDA Currents.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	CEDA, technical council, EDA, electronic design automation
2		CEDA Currents.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	CEDA, technical council, EDA, electronic design automation
2		CEDA Currents.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	CEDA, technical council, EDA, electronic design automation
2	Jasjeet Kaur	A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company.	ISQED	2005	DBLP DOI BibTeX RDF
2	Stephen Dawson, Sakir Sezer	Web Based Service Provision - A Case Study: Electronic Design Automation.	ICT	2004	DBLP DOI BibTeX RDF
2	Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams	An industrial view of electronic design automation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	João P. Marques Silva, Karem A. Sakallah	Boolean satisfiability in electronic design automation.	DAC	2000	DBLP DOI BibTeX RDF
2	Karen C. Davis, Satish Venkatesan, Lois M. L. Delcambre	Sharing Electronic Design Data Via Semantic Spaces.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	design databases, data exchange, electronic design automation
2	Amir A. Khwaja	Enhancing extensibility of the design rule checker of an EDA tool by object-oriented modeling. (PDF / PS)	COMPSAC	1997	DBLP DOI BibTeX RDF	design rule checker, design rule checking systems, electronic design automation tools, semiconductor technology, DRC systems, DRC module, IC package design tool, object oriented modeling technique, abstraction, inheritance, extensibility, object oriented modeling, encapsulation, circuit CAD, dynamic binding, EDA tool
2	Mike Newman, Tom Rhyne (eds.)	Electronic Design Automation Frameworks: When will the promise be realized? Proceedings of the Third IFIP WG10.2/WG10.5 Workshop on Electronic Design Automation Frameworks in cooperation with GI/ITG FG 3.5.6/5.2.6 Bad Lippspringe, Germany, 23-25 March, 1992	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Flávio Rech Wagner, Lia Goldstein Golendziner, Jean Lacombe, Arnaldo Hilário Viegas de Lima	Design Version Management in the STAR Framework.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	B. Després, M. N. Lipp, Robert Piloty, U. Schellin	Structural Consistency Support in an Integral Design System.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	M. Rumsey, Neil Crofts, Bob Luckin, Colin Farquhar	Measuring Frameworks.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Idalina Videira, Helena Sarmento	Tool Integration Made Easier.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Wolfgang Wilkes, Gerhard Scholz	Different Levels of Information Models for Use in Frameworks.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	J. Bloedel, M. Brandstetter, Peter Conradi, W. Drangmeister, Reiner W. Hartenstein, D. Schroeder	An Information Model Describing the Exchange of IC Technology Data.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Bernd Steinmüller	The JESSI-COMMON-FRAME Project - A Project Overview.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Jim Heaton	The JESSI-COMMON-FRAME Project SP4 Evaluation: Evaluating the Options.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Günter von Bültzingsloewen	JCF Applied Framework Research - An Overview.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Susan A. Dart	Parallels in Computer-Aided Design Framework and Software Development Environment Efforts.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	João Martins, João Camara, Helena Sarmento	User Interaction in a Silicon Compilation Environment.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Uwe Jasnoch	Global Consistency Management Within a CAD Framework.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Werner John, D. Pörtner	A Framework-Solution for the EMC-Analysis-Domain Based on Graphical Integration-Schema.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Thomas Kathöfer, J. Miller	The JESSI-COMMON-FRAME Project - Sub-project Development.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Jay B. Brockman, Stephen W. Director	A Schema-Based Approach to CAD Task Management.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Elisabeth Kupitz	Design Assistance in Concurrent Integrated Environments	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Tom Rhyne	ECAD Design Technology-Where Does it Stand?	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	Olav Schettler, Ansgar Bredenfeld	Handling Schema Information in the DASSY Data Model.	Electronic Design Automation Frameworks	1992	DBLP BibTeX RDF
2	A. Richard Newton	Twenty-Five Years of Electronic Design Automation.	DAC	1988	DBLP BibTeX RDF
1	John Lee, Puneet Gupta	Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment.	Foundations and Trends in Electronic Design Automation	2012	DBLP DOI BibTeX RDF
1	Igor L. Markov	EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)].	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie	Three-dimensional Integrated Circuits: Design, EDA, and Architecture.	Foundations and Trends in Electronic Design Automation	2011	DBLP DOI BibTeX RDF
1	John Sartori, Rakesh Kumar	Stochastic Computing.	Foundations and Trends in Electronic Design Automation	2011	DBLP BibTeX RDF
1	Peng Li	Parallel Circuit Simulation: A Historical Perspective and Recent Developments.	Foundations and Trends in Electronic Design Automation	2011	DBLP DOI BibTeX RDF
1	Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao	System-in-Package: Electrical and Layout Perspectives.	Foundations and Trends in Electronic Design Automation	2011	DBLP DOI BibTeX RDF
1	Norbert Seifert	Radiation-induced Soft Errors: A Chip-level Modeling Perspective.	Foundations and Trends in Electronic Design Automation	2010	DBLP DOI BibTeX RDF
1	David Z. Pan, Minsik Cho, Kun Yuan	Manufacturability Aware Routing in Nanometer VLSI.	Foundations and Trends in Electronic Design Automation	2010	DBLP DOI BibTeX RDF
1	Ruchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok	EDA challenges and options: investing for the future.	DAC	2010	DBLP DOI BibTeX RDF	design challenges, electronic design automation
1	Jagannath Keshava, Nagib Hakim, Chinna Prudvi	Post-silicon validation challenges: how EDA and academia can help.	DAC	2010	DBLP DOI BibTeX RDF	design, verification, test, validation, emulation
1	Lijuan Luo, Martin D. F. Wong, Wen-mei W. Hwu	An effective GPU implementation of breadth-first search.	DAC	2010	DBLP DOI BibTeX RDF	BFS, CUDA, GPU computing
1	Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici	Post-silicon validation opportunities, challenges and recent advances.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon validation
1	Marc Riedel, Soha Hassoun, Ron Weiss, Pamela Silver, J. Christopher Anderson, Richard M. Murray	Joint DAC/IWBDA special session engineering biology: fundamentals and applications.	DAC	2010	DBLP DOI BibTeX RDF	bio-design automation, biological circuits, cellular programming, robustness, control, feedback, computational biology, system biology, modular designs, synthetic biology
1	Jun Wu, Yong-Bin Kim, Minsu Choi	Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	substitution box, substitution box (S-box), differential power/noise analysis, power/noise measurement, security, advanced encryption standard, advanced encryption standard, side-channel attacks (SCA), null convention logic
1	Jaijeet S. Roychowdhury	Numerical Simulation and Modelling of Electronic and Biochemical Systems.	Foundations and Trends in Electronic Design Automation	2009	DBLP DOI BibTeX RDF
1	Harry Foster	Applied Assertion-Based Verification: An Industry Perspective.	Foundations and Trends in Electronic Design Automation	2009	DBLP DOI BibTeX RDF
1	Radu Marculescu, Paul Bogdan	The Chip Is the Network: Toward a Science of Network-on-Chip Design.	Foundations and Trends in Electronic Design Automation	2009	DBLP DOI BibTeX RDF
1	Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao	The Predictive Technology Model in the Late Silicon Era and Beyond.	Foundations and Trends in Electronic Design Automation	2009	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Valeria Bertacco	Human computing for EDA.	DAC	2009	DBLP DOI BibTeX RDF	satisfiability, human computing
1	Rajdeep Mukhopadhyay, S. K. Panda, Pallab Dasgupta, John Gough	Instrumenting AMS assertion verification on commercial platforms.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
1	Maman Abdurohman, Kuspriyanto, Sarwono Sutikno, Arif Sasongko	Transaction Level Modeling for Early Verification on Embedded System Design.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
1	Unmesh D. Bordoloi, Samarjit Chakraborty	Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
1	Constantinos Kotsokalis, Ramin Yahyapour, Miguel Angel Rojas Gonzalez	Modeling Service Level Agreements with Binary Decision Diagrams.	ICSOC/ServiceWave	2009	DBLP DOI BibTeX RDF
1	Robert Nieuwenhuis	SAT Modulo Theories: Enhancing SAT with Special-Purpose Algorithms.	SAT	2009	DBLP DOI BibTeX RDF
1	Giuseppe Nicosia, Giovanni Stracquadanio	A Design-for-Yield Algorithm to Assess and Improve the Structural and Energetic Robustness of Proteins and Drugs.	SEA	2009	DBLP DOI BibTeX RDF
1	Yiming Li, Shao-Ming Yu, Yih-Lang Li	Electronic design automation using a unified optimization framework.	Mathematics and Computers in Simulation	2008	DBLP DOI BibTeX RDF
1	Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar	Thermally Aware Design.	Foundations and Trends in Electronic Design Automation	2008	DBLP DOI BibTeX RDF
1	João Marques-Silva, Jordi Planes	Algorithms for Maximum Satisfiability using Unsatisfiable Cores.	DATE	2008	DBLP DOI BibTeX RDF
1	Jiangbo Qian, Rangding Wang, Guang Jin, Yuan Li	Breaking Boundaries among Hardware Curriculums by EDA Technology.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li	Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Helmut Simonis, Barry O'Sullivan	Search Strategies for Rectangle Packing.	CP	2008	DBLP DOI BibTeX RDF
1	Mile K. Stojcev	Louis Scheffer, Luciano Lavagno and Grant Martin, Editors, Electronic Design Automation for Integrated Circuits Handbook Vols. I and II, CRC, imprint of Taylor and Francis Group, Boca Raton (2006) ISBN 0-8493-3096-3 Hardcover, 1095 pp., plus XLVIII.	Microelectronics Reliability	2007	DBLP DOI BibTeX RDF
1	Alexander Taubin, Jordi Cortadella, Luciano Lavagno, Alex Kondratyev, Ad M. G. Peeters	Design Automation of Real-Life Asynchronous Devices and Systems.	Foundations and Trends in Electronic Design Automation	2007	DBLP DOI BibTeX RDF
1	Ian Kuon, Russell Tessier, Jonathan Rose	FPGA Architecture: Survey and Challenges.	Foundations and Trends in Electronic Design Automation	2007	DBLP DOI BibTeX RDF
1	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
1	Lei Fang, Michael S. Hsiao	A new hybrid solution to boost SAT solver performance.	DATE	2007	DBLP DOI BibTeX RDF
1	Ajay K. Verma, Paolo Ienne	Automatic synthesis of compressor trees: reevaluating large counters.	DATE	2007	DBLP DOI BibTeX RDF
1	Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko	Scalable exploration of functional dependency by interpolation and incremental SAT solving.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Aashish Phansalkar, Ajay Joshi, Lizy Kurian John	Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite.	ISCA	2007	DBLP DOI BibTeX RDF	microprocessor performance counters, clustering, benchmark, SPEC
1	Alexander Pacholik, Wolfgang Fengler	A system model for formal verification of TLM based transaction properties.	SpringSim	2007	DBLP DOI BibTeX RDF	Petri nets, formal verification, temporal logic, discrete event systems
1	Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, José Luis Pino	Efficient simulation of critical synchronous dataflow graphs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	simulation, Scheduling, synchronous dataflow
1	Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka	A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery.	DSN	2007	DBLP DOI BibTeX RDF
1	Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer	Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Jimin Feng, Samarjit Chakraborty, Bertil Schmidt, Weiguo Liu, Unmesh D. Bordoloi	Fast Schedulability Analysis Using Commodity Graphics Hardware.	RTCSA	2007	DBLP DOI BibTeX RDF
1	Zhaohui Fu, Sharad Malik	Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Fadi A. Aloul, Arathi Ramani, Karem A. Sakallah, Igor L. Markov	Solution and Optimization of Systems of Pseudo-Boolean Constraints.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Pseudo Boolean (PB), Max-ONE, Global Routing, Conjunctive Normal Form (CNF), Backtrack Search, Integer Linear Programming (ILP), Max-SAT, Boolean Satisfiability (SAT)
1	Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu	STEAC: A Platform for Automatic SOC Test Integration.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Bruce W. Watson	Automata Applications in Chip-Design Software.	CIAA	2007	DBLP DOI BibTeX RDF	design rule checking, pattern matching, EDA, integrated circuit layout, chip design
1	Xin Li, Jiayong Le, Lawrence T. Pileggi	Statistical Performance Modeling and Optimization.	Foundations and Trends in Electronic Design Automation	2006	DBLP DOI BibTeX RDF
1	Deming Chen, Jason Cong, Peichen Pan	FPGA Design Automation: A Survey.	Foundations and Trends in Electronic Design Automation	2006	DBLP DOI BibTeX RDF
1	Luca P. Carloni, Roberto Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli	Languages and Tools for Hybrid Systems Design.	Foundations and Trends in Electronic Design Automation	2006	DBLP DOI BibTeX RDF
1	Jürgen Teich	Are current ESL tools meeting the requirements of advanced embedded systems?	CODES+ISSS	2006	DBLP DOI BibTeX RDF	behavioral and system synthesis, electronic system level (ESL) design, electronic design automation
1	Chia-Jui Hsu, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, Shuvra S. Bhattacharyya	Efficient simulation of critical synchronous dataflow graphs.	DAC	2006	DBLP DOI BibTeX RDF	simulation, scheduling, synchronous dataflow
1	Zhaohui Fu, Sharad Malik	Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search.	ICCAD	2006	DBLP DOI BibTeX RDF	MinCostSAT, optimization, branch-and-bound, Boolean satisfiability
1	Kun Tong, Jinian Bian, Haili Wang	Universal data model platform: the data-centric evolution for system level codesign.	CSCWD	2006	DBLP DOI BibTeX RDF
1	Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida	Fast timing analysis of plane circuits via two-layer CNN-based modeling.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander	Automated Architectural Exploration for Signal Processing Algorithms.	SiPS	2006	DBLP DOI BibTeX RDF
1	Yervant Zorian, Dennis Wassung	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
1	Scott Davidson	Book Reviews: A Comprehensive EDA Handbook.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	EDA, book review
1		CEDA Currents.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	Robert Brayton, IEEE Emanuel R. Piore Award
1	Görschwin Fey, Rolf Drechsler	Minimizing the number of paths in BDDs: Theory and algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky	Computer-Aided Optimization of DNA Array Design and Manufacturing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Vivek V. Shende, Stephen S. Bullock, Igor L. Markov	Synthesis of quantum-logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF