Search results for "Eli Bozorgzadeh"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh	SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker	Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010).	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Shahin Golshan, Love Singhal, Eli Bozorgzadeh	Process variation aware system-level load assignment for total energy minimization using stochastic ordering.	ISQED	2011	DBLP DOI BibTeX RDF
1	Hessam Kooti, Deepak Mishra, Eli Bozorgzadeh	Reconfiguration-aware real-time scheduling under QoS constraint.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt	Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.	TRETS	2010	DBLP DOI BibTeX RDF
1	Hessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, Lichun Bao	Transition-aware real-time task scheduling for reconfigurable embedded systems.	DATE	2010	DBLP BibTeX RDF
1	Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.	ISQED	2010	DBLP DOI BibTeX RDF
1	Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum	Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.	ISLPED	2010	DBLP DOI BibTeX RDF	computer aided design, placement, dynamic reconfiguration, temperature, reconfigurable systems
1	Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu	Welcome message.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Hessam Kooti, Eli Bozorgzadeh, Shenghui Liao, Lichun Bao	Reconfiguration-aware spectrum sharing for FPGA based software defined radio.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Hessam Kooti, Eli Bozorgzadeh	Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCs.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Shahin Golshan, Eli Bozorgzadeh	SEU-aware resource binding for modular redundancy based designs on FPGAs.	DATE	2009	DBLP BibTeX RDF
1	Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Process variation aware system-level task allocation using stochastic ordering of delay distributions.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao	Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs.	ICCD	2008	DBLP DOI BibTeX RDF
1	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Statistical power profile correlation for realistic thermal estimation.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield
1	Love Singhal, Elaheh Bozorgzadeh, David Eppstein	Interconnect Criticality-Driven Delay Relaxation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Multi-layer floorplanning for reconfigurable designs.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Novel Multi-Layer floorplanning for Heterogeneous FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera	Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.	DAC	2007	DBLP DOI BibTeX RDF
1	Shahin Golshan, Elaheh Bozorgzadeh	Single-Event-Upset (SEU) Awareness in FPGA Routing.	DAC	2007	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Heterogeneous Floorplanner for FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
1	Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee	Energy-aware co-processor selection for embedded processors on FPGAs.	ICCD	2007	DBLP DOI BibTeX RDF
1	Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh	A Unified Theory of Timing Budget Management.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh	Statistical Analysis and Design of HARP FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	FABSYN: floorplan-aware bus architecture synthesis.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Soheil Ghiasi, Elaheh Bozorgzadeh, Karlene Nguyen, Majid Sarrafzadeh	Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	accuracy-latency tradeoff, delay budgeting, object tracking, collaborative applications
1	Love Singhal, Elaheh Bozorgzadeh	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.	FPL	2006	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Physically-aware exploitation of component reuse in a partially reconfigurable architecture.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt	PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.	ASP-DAC	2006	DBLP DOI BibTeX RDF	granularity selection, linear placement, scheduling, data-parallelism, partial dynamic reconfiguration
1	S. Dai, Elaheh Bozorgzadeh	CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures.	FCCM	2006	DBLP DOI BibTeX RDF
1	Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	A scheduling algorithm for optimization and early planning in high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Scheduling, high-level synthesis, data flow graph, bipartite matching
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.	DAC	2005	DBLP DOI BibTeX RDF	HW-SW partitioning, linear placement, partial dynamic reconfiguration
1	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	Floorplan-aware automated synthesis of bus-based communication architectures.	DAC	2005	DBLP DOI BibTeX RDF	systems-on-chip, communication synthesis
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.	FCCM	2005	DBLP DOI BibTeX RDF
1	Love Singhal, Elaheh Bozorgzadeh	Fast timing closure by interconnect criticality driven delay relaxation.	ICCAD	2005	DBLP BibTeX RDF
1	Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh	HARP: hard-wired routing pattern FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh	Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs.	Journal of Circuits, Systems, and Computers	2004	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh	Optimal integer delay-budget assignment on directed acyclic graphs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh	Incremental Timing Budget Management in Programmable Systems.	ERSA	2004	DBLP BibTeX RDF
1	Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh	A unified theory of timing budget management.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh	Creating and exploiting flexibility in rectilinear Steiner trees.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh	Optimal integer delay budgeting on directed acyclic graphs.	DAC	2003	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Majid Sarrafzadeh	Customized regular channel design in FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
1	Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh	On computation and resource management in an FPGA-based computation environment.	FPGA	2003	DBLP DOI BibTeX RDF
1	Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh	Budget Management with Applications.	Algorithmica	2002	DBLP DOI BibTeX RDF
1	Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh	Instruction generation for hybrid reconfigurable systems.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, high-level synthesis, reconfigurable computing
1	Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Pattern routing: use and theory for increasing predictability andavoiding coupling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava	Design and analysis of physical design algorithms.	ISPD	2001	DBLP DOI BibTeX RDF
1	Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	An exact algorithm for coupling-free routing.	ISPD	2001	DBLP DOI BibTeX RDF
1	Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Wirelength estimation based on rent exponents of partitioning and placement.	SLIP	2001	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh	Creating and Exploiting Flexibility in Steiner Trees.	DAC	2001	DBLP DOI BibTeX RDF
1	Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh	RPack: routability-driven packing for cluster-based FPGAs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh	A Super-Scheduler for Embedded Reconfigurable Systems.	ICCAD	2001	DBLP BibTeX RDF
1	Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Instruction Generation for Hybrid Reconfigurable Systems.	ICCAD	2001	DBLP BibTeX RDF
1	Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	Predictable Routing.	ICCAD	2000	DBLP BibTeX RDF

Publications of Eli Bozorgzadeh Elaheh Bozorgzadeh ( http://dblp.L3S.de/Authors/Eli_Bozorgzadeh )