Search results for "Elias Kougianos"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan	Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.	Integration	2012	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization.	ISQED	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah	Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications.	ISQED	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng	Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Real-time perceptual watermarking architectures for video broadcasting.	Journal of Systems and Software	2011	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling.	ISQED	2011	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil	Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos	DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Yu-Ting Pai, Li-Te Lee, Shanq-Jang Ruan, Yen-Hsiang Chen, Saraju P. Mohanty, Elias Kougianos	Honeycomb model based skin colour detector for face detection.	IJCAT	2010	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos	A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty	Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty, Rabi N. Mahapatra	Hardware assisted watermarking for multimedia.	Computers & Electrical Engineering	2009	DBLP DOI BibTeX RDF
1	Vijay V. Vaidyanathan, Murali R. Varanasi, Elias Kougianos, Shuping Wang, Hari Raman	RFID Student Educational Experiences at the UNT College of Engineering: A Sequential Approach to Creating a Project-Based RFID Course.	IEEE Trans. Education	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments.	ISQED	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani	VLSI architectures of perceptual based video watermarking for real-time copyright protection.	ISQED	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi	A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems.	ISQED	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra	A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.	ISQED	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
1	Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan	Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs.	ISQED	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.	ISQED	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
1	Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan	VLSI architecture and chip for combined invisible robust and fragile watermarking.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty	Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Cheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mikler, Elias Kougianos, Brandon Parker	A High Performance ASIC for Cellular Automata (CA) Applications.	ICIT	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.	ISQED	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty	Effective tunneling capacitance: a new metric to quantify transient gate leakage current.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee	Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Parthasarathy Guturu, Elias Kougianos, Nishikanta Pati	A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction.	ISM	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates.	ICCD	2006	DBLP BibTeX RDF
1	Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos	A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits.	ICCD	2005	DBLP DOI BibTeX RDF

Publications of "Elias Kougianos" ( http://dblp.L3S.de/Authors/Elias_Kougianos )