Search results for "Elio Consoli"

Found 15 publication records. Showing 15 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link
1	Elio Consoli, Gaetano Palumbo, Melita Pennisi	Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo	An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey	Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo	Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo	An ultra-compact MOS model in nanometer technologies.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Elio Consoli, Gaetano Palumbo, Melita Pennisi	TG Master-Slave FFs: High-speed optimization.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	DET FF topologies: A detailed investigation in the energy-delay-area domain.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Massimo Alioto, Elio Consoli, Gaetano Palumbo	Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.	ICECS	2009	DBLP DOI BibTeX RDF

Publications of "Elio Consoli" ( http://dblp.L3S.de/Authors/Elio_Consoli )