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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4 occurrences of 4 keywords
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Results
Found 37 publication records. Showing 37 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floch, Krzysztof Kuchcinski, Stéphane Chevobbe, Stéphane Guyetant |
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture.  |
IJERTCS  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenglong Xiao, Emmanuel Casseau |
Exact custom instruction enumeration for extensible processors. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Emmanuel Casseau, Bertrand Le Gal |
Design of multi-mode application-specific cores based on high-level synthesis. |
Integration |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bertrand Le Gal, Emmanuel Casseau |
Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. |
EURASIP J. Adv. Sig. Proc. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bertrand Le Gal, Emmanuel Casseau |
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Daniel Menard, Hai-Nam Nguyen, François Charot, Stéphane Guyetant, Jérémie Guillot, Erwan Raffin, Emmanuel Casseau |
Exploiting reconfigurable SWP operators for multimedia applications. |
ICASSP |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrei Banciu, Emmanuel Casseau, Daniel Menard, Thierry Michel |
Stochastic modeling for floating-point to fixed-point conversion. |
SiPS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Hervé Yviquel, Emmanuel Casseau, Matthieu Wipliez, Mickaël Raulet |
Efficient multicore scheduling of dataflow process networks. |
SiPS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenglong Xiao, Emmanuel Casseau |
Efficient maximal convex custom instruction enumeration for extensible processors. |
DASIP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chenglong Xiao, Emmanuel Casseau |
An efficient algorithm for custom instruction enumeration. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenglong Xiao, Emmanuel Casseau |
Efficient custom instruction enumeration for extensible processors. |
ASAP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet |
High-Level Synthesis for Designing Multimode Architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer |
A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. |
DASIP |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Andrei Banciu, Emmanuel Casseau, Daniel Menard, Thierry Michel |
A case study of the stochastic modeling approach for range estimation. |
DASIP |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau |
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. |
DASIP |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Emmanuel Casseau, Bertrand Le Gal |
High-level synthesis for the design of FPGA-based signal processing systems. |
ICSAMOS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Shafqat Khan, Emmanuel Casseau, Daniel Menard |
Reconfigurable SWP Operator for Multimedia Processing. |
ASAP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David |
Reconfigurable Operator Based Multimedia Embedded Processor. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet |
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina |
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. |
Technique et Science Informatiques |
2008 |
DBLP BibTeX RDF |
|
| 1 | Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin |
Constrained algorithmic IP design for system-on-chip. |
Integration |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy |
Synthesis of Multimode digital signal processing systems. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sylvain Huet, Sébastien LeNours, Olivier Pasquier, Emmanuel Casseau |
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. |
FDL |
2007 |
DBLP BibTeX RDF |
|
| 1 | Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin |
A design flow dedicated to multi-mode architectures for DSP applications. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
flexible devices, multi-mode architectures, high-level synthesis |
| 1 | Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin |
A formal method for hardware IP design and integration under I/O and timing constraints. |
ACM Trans. Embedded Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
IP design and integration, communication interface unit, constrained synthesis, digital signal processing and multimedia applications, SoC |
| 1 | Guillaume Savaton, Emmanuel Casseau, Eric Martin |
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. |
Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin |
G729 Voice Decoder Design. |
VLSI Signal Processing |
2006 |
DBLP DOI BibTeX RDF |
CELP coders, G729 standard, Hw/Sw design, LPC analysis, voice decoding, IP, VLSI design |
| 1 | Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau |
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sylvain Huet, Emmanuel Casseau, Olivier Pasquier |
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sylvain Huet, Emmanuel Casseau, Olivier Pasquier, Sébastien LeNours |
Hardware Communication Refinement in Digital Signal Processing. |
FDL |
2006 |
DBLP BibTeX RDF |
|
| 1 | Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin |
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sylvain Huet, Emmanuel Casseau, Olivier Pasquier |
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno |
Hardware Virtual Components Compliant with Communication System Standards. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Emmanuel Casseau, Christophe Jégo, Eric Martin |
Synthèse architecturale d'applications temps réel pour technologies submicroniques. |
Technique et Science Informatiques |
2004 |
DBLP BibTeX RDF |
|
| 1 | Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin |
Reed-Solomon behavioral virtual component for communication systems. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Christophe Jégo, Emmanuel Casseau, Eric Martin |
Architectural Synthesis with Interconnection Cost Control. |
VLSI |
1999 |
DBLP BibTeX RDF |
|
| 1 | Emmanuel Casseau, Dominique Degrugillier |
A Linear Systolic Array for LU Decomposition. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
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Displaying result #1 - #37 of 37 (100 per page; Change: )
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