Search results for "Emrah Acar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Amith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal	DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM.	ISQED	2012	DBLP DOI BibTeX RDF
1	Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton	Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer	Abstraction and microarchitecture scaling in early-stage power modeling.	HPCA	2011	DBLP DOI BibTeX RDF
1	Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar	Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das	Yield estimation of SRAM circuits using "Virtual SRAM Fab".	ICCAD	2009	DBLP BibTeX RDF
1	Haifeng Qian, Emrah Acar	Timing-Aware Power Minimization via Extended Timing Graph Methods.	J. Low Power Electronics	2007	DBLP DOI BibTeX RDF
1	Peng Li, Zhuo Feng, Emrah Acar	Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
1	Emrah Acar, Peter Feldmann	Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA).	ISCAS	2006	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Kanak Agarwal, Emrah Acar	Methods for estimating decoupling capacitance of nonswitching circuit blocks.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Emrah Acar, Kanak Agarwal, Sani R. Nassif	Characterization of total chip leakage using inverse (reciprocal) gamma distribution.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Emrah Acar, Anirudh Devgan, Sani R. Nassif	Leakage and Leakage Sensitivity Computation for Combinational Circuits.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Peng Li, Emrah Acar	A Waveform Independent Gate Model for Accurate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
1	Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif	Optimal shielding/spacing metrics for low power design.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns	Leakage and leakage sensitivity computation for combinational circuits.	ISLPED	2003	DBLP DOI BibTeX RDF	iddq analysis, sensitivity, power estimation, leakage power
1	Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif	Full chip leakage estimation considering power supply and temperature variations.	ISLPED	2003	DBLP DOI BibTeX RDF	supply voltage variation, leakage power, thermal analysis
1	Haihua Su, Emrah Acar, Sani R. Nassif	Power grid reduction based on algebraic multigrid principles.	DAC	2003	DBLP DOI BibTeX RDF	AC analysis, transient analysis, algebraic multigrid, power grid noise
1	Emrah Acar, Florentin Dartu, Lawrence T. Pileggi	TETA: transistor-level waveform evaluation for timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi	Time-Domain Simulation of Variational Interconnect Models. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	simulation, Interconnect, variational models, reduced order modeling
1	Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi	A Linear-Centric Simulation Framework for Parametric Fluctuations.	DATE	2002	DBLP DOI BibTeX RDF
1	Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu	Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.	ISQED	2001	DBLP DOI BibTeX RDF
1	Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Tao Lin, Emrah Acar, Lawrence T. Pileggi	h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response.	ICCAD	1998	DBLP DOI BibTeX RDF

Publications of "Emrah Acar" ( http://dblp.L3S.de/Authors/Emrah_Acar )