Search results for "Energy reduction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur	Energy Reduction in SRAM using Dynamic Voltage and Frequency Management.	VLSI Design	2008	DBLP DOI BibTeX RDF	Delay Monitor, DVFM, Pareto optimal curve, Replica circuits, SRAM, Energy reduction, Energy monitor
3	Slo-Li Chu	POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture.	ICPADS	2005	DBLP DOI BibTeX RDF	POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction
2	Soontae Kim, Jongmin Lee 0002	Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, data cache, write buffer
2	Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek	Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Toshinori Sato, Yuji Kunitake	Exploiting Input Variations for Energy Reduction.	PATMOS	2007	DBLP DOI BibTeX RDF	typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron
2	Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino	Locality-driven architectural cache sub-banking for leakage energy reduction.	ISLPED	2007	DBLP DOI BibTeX RDF	banked cache, memory hierarchy, leakage reduction, architectural optimization
2	K. Shyam, R. Govindarajan	An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures.	CC	2007	DBLP DOI BibTeX RDF
2	Changjiu Xian, Yung-Hsiang Lu	Energy reduction by workload adaptation in a multi-process environment.	DATE	2006	DBLP DOI BibTeX RDF
2	Xia Xiao Xin, Tay Teng Tiow	IPC-driven energy reduction for low-power design.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Lin Yuan, Gang Qu	Analysis of energy reduction on dynamic voltage scaling-enabled systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Aviral Shrivastava, Ilya Issenin, Nikil Dutt	Compilation techniques for energy reduction in horizontally partitioned cache architectures.	CASES	2005	DBLP DOI BibTeX RDF	XScale, horizontally-partitioned cache, mini-cache, split cache, compiler, energy, data cache
2	Lin Xie, Peiliang Qiu, Qinru Qiu	Partitioned bus coding for energy reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
2	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Aggregating processor free time for energy reduction.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	processor free time, embedded systems, aggregation, clock gating, code transformation, energy reduction
2	Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato	A leakage-energy-reduction technique for highly-associative caches in embedded systems.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF	cache memories, embedded processors, leakage current
2	Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Isolating Short-Lived Operands for Energy Reduction.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
2	Chia-Lin Yang, Chien-Hao Lee	HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.	ISLPED	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, instruction cache
2	Masaharu Goto, Toshinori Sato	Leakage Energy Reduction in Register Renaming.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy
2	Michael C. Huang, Jose Renau, Josep Torrellas	Positional Adaptation of Processors: Application to Energy Reduction. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
2	Mitali Singh, Viktor K. Prasanna	Algorithmic Techniques for Memory Energy Reduction.	WEA	2003	DBLP DOI BibTeX RDF
2	Paul-Peter Sotiriadis, Anantha Chandrakasan, Vahid Tarokh	Maximum achievable energy reduction using coding with applications to deep sub-micron buses.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai	Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.	MICRO	2001	DBLP DOI BibTeX RDF
2	P. R. van der Meer, Arie van Staveren	Effectivity of standby-energy reduction techniques for deep sub-micron CMOS.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
2	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
1	Lovic Gauthier, Tohru Ishihara	Processor Energy Characterization for Compiler-Assisted Software Energy Reduction.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, O. Mencer	Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González	Compiler Directed Issue Queue Energy Reduction.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Jae-Wan Jang, Myeongjae Jeon, Hyo-Sil Kim, Heeseung Jo, Jin-Soo Kim, Seungryoul Maeng	Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Jian (Denny) Lin, Albert M. K. Cheng	Energy reduction for scheduling a set of multiple feasible interval jobs.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Sourya Roy, Tyler Clemons, S. M. Faisal, Ke Liu, Nikos Hardavellas, Srinivasan Parthasarathy	Elastic Fidelity: Trading-off Computational Accuracy for Energy Reduction	CoRR	2011	DBLP BibTeX RDF
1	Olle Svanfeldt-Winter, Sébastien Lafond, Johan Lilius	Cost and Energy Reduction Evaluation for ARM Based Web Servers.	DASC	2011	DBLP DOI BibTeX RDF
1	Jongmin Lee 0002, Seokin Hong, Soontae Kim	TLB index-based tagging for cache energy reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Yebin Lee, Soontae Kim	DRAM energy reduction by prefetching-based memory traffic clustering.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu	A novel energy reduction technique for H.264 intra mode decision.	ICIP	2011	DBLP DOI BibTeX RDF
1	Cedric Levy-Bencheton, Guillaume Vtllemaud, Tanguy Risset	Toward an energy reduction in mobile relays: Combining MIMO and multi-mode.	Wireless Days	2011	DBLP DOI BibTeX RDF
1	Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami	Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.	ARC	2011	DBLP DOI BibTeX RDF
1	Antonio González	Moore's law implications on energy reduction.	HiPEAC	2011	DBLP DOI BibTeX RDF
1	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Energy reduction with run-time partial reconfiguration (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, energy
1	Vasily G. Moshnyaga	The use of eye tracking for PC energy management.	ETRA	2010	DBLP DOI BibTeX RDF	eye tracking, applications, energy reduction
1	Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal	Xetal-Pro: an ultra-low energy and high throughput SIMD processor.	DAC	2010	DBLP DOI BibTeX RDF	Xetal-Pro, hybrid memory system, SIMD, low-energy
1	Chen Huang, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Aging effects of leakage optimizations for caches.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	memory hierarchy, aging, leakage reduction
1	Hai Lin 0004, Yunsi Fei	A novel multi-objective instruction synthesis flow for application-specific instruction set processors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	instruction set synthesis, application-specific instruction set processor (ASIP)
1	Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija	Energy efficient implementation of parallel CMOS multipliers with improved compressors.	ISLPED	2010	DBLP DOI BibTeX RDF	arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding
1	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Resilient microprocessor design for high performance & energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	resilient design
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Dynamic indexing: concurrent leakage and aging optimization for caches.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage optimization, memory hierarchy, aging, NBTI
1	Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio	MODEST: a model for energy estimation under spatio-temporal variability.	ISLPED	2010	DBLP DOI BibTeX RDF	dsm scaling, spatio-temporal variability, cache design
1	Carlos Santana, Julius C. B. Leite, Daniel Mossé	Load forecasting applied to soft real-time web clusters.	SAC	2010	DBLP DOI BibTeX RDF	web server cluster, QoS, power management, energy consumption, dynamic configuration, load forecasting
1	Xiao Xin Xia, Teng Tiow Tay	Intra-Application Energy Reduction for Microprocessor Low-Power Design.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Chun-Mok Chung, Jihong Kim	Broadcast filtering: Snoop energy reduction in shared bus-based low-power MPSoCs.	Journal of Systems Architecture - Embedded Systems Design	2009	DBLP DOI BibTeX RDF
1	Young Choon Lee, Albert Y. Zomaya	On Effective Slack Reclamation in Task Scheduling for Energy Reduction.	JIPS	2009	DBLP DOI BibTeX RDF
1	Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo, Lothar Thiele	Energy Reduction Techniques for Systems with non-DVS Components.	ETFA	2009	DBLP DOI BibTeX RDF
1	Lovic Gauthier, Tohru Ishihara	Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories.	ESTImedia	2009	DBLP DOI BibTeX RDF
1	Ping Zhou, Bo Zhao, Jun Yang 0002, Youtao Zhang	Energy reduction for STT-RAM using early write termination.	ICCAD	2009	DBLP BibTeX RDF
1	Stefan Valentin Gheorghita, Martin Palkovic, Juan Hamers, Arnout Vandecappelle, Stelios Mamagkakis, Twan Basten, Lieven Eeckhout, Henk Corporaal, Francky Catthoor, Frederik Vandeputte, Koen De Bosschere	System-scenario-based design of dynamic embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	dynamic nature, system scenarios, real-time systems, embedded systems, Design methodology, energy reduction
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
1	Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic	HitME: low power Hit MEmory buffer for embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Lillian Smith, Frame Demchak	Project Chicago: green research.	CHI Extended Abstracts	2009	DBLP DOI BibTeX RDF	input and interaction, user experience design/ experience design, visualization, collaboration, interaction design, graphical user interface, technologies, sustainability, product design
1	Mohammad Ali Ghodrat, Tony Givargis	Efficient dynamic voltage/frequency scaling through algorithmic loop transformation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	algorithmic loop transformation, compiler optimization for low power, dynamic voltage/frequency scaling
1	Jianwei Dai, Lei Wang 0003	Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy.	ISLPED	2009	DBLP DOI BibTeX RDF	low-power technique, way-tag array, cache
1	Michael J. Lyons, David Brooks	The design of a bloom filter hardware accelerator for ultra low power systems.	ISLPED	2009	DBLP DOI BibTeX RDF	wireless sensor network, hardware accelerator, bloom filter
1	Balaji V. Iyer, Thomas M. Conte	On power and energy trends of IEEE 802.11n PHY.	MSWiM	2009	DBLP DOI BibTeX RDF	power and energy characterization, IEEE 802.11n
1	Martin Palkovic, Francky Catthoor, Henk Corporaal	Trade-offs in loop transformations.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Data transfer and storage exploration, cost components, optimization, loop transformations, trade-offs
1	Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang 0002	A low-radix and low-diameter 3D interconnection network design.	HPCA	2009	DBLP DOI BibTeX RDF
1	Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek	Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Jungsoo Kim, Seungyong Oh, Sungjoo Yoo, Chong-Min Kyung	An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron	Memory MISER: Improving Main Memory Energy Efficiency in Servers.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Edward T.-H. Chu, Tai-Yi Huang, Cheng-Han Tsai, Jian-Jia Chen, Tei-Wei Kuo	A DVS-assisted hard real-time I/O device scheduling algorithm.	Real-Time Systems	2009	DBLP DOI BibTeX RDF	Dynamic voltage scaling, Dynamic power management, Real-time embedded systems
1	Pepijn J. de Langen, Ben H. H. Juurlink	Leakage-Aware Multiprocessor Scheduling.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Scheduling, Multiprocessor, Leakage power, Voltage scaling
1	Meikang Qiu, Meiqin Liu, Hao Li, Hung-Chung Huang, Wenyuan Li, Jiande Wu	Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Optimization, Real-time, Multi-core, Assignment, Loop scheduling
1	Ranjith Kumar, Volkan Kursun	Temperature-Adaptive Energy Reduction Techniques for Nano-CMOS Circuits Displaying Reversed temperature Dependence.	Journal of Circuits, Systems, and Computers	2008	DBLP DOI BibTeX RDF
1	Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cristian Grecu	Energy reduction through crosstalk avoidance coding in networks on chip.	Journal of Systems Architecture - Embedded Systems Design	2008	DBLP DOI BibTeX RDF
1	Silvia Del Pino, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado	Energy reduction of the fetch mechanism through dynamic adaptation.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Vasily G. Moshnyaga	Untraditional Approach to Computer Energy Reduction.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Jongeun Lee, Aviral Shrivastava	Static analysis of processor stall cycle aggregation.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	memory bound loops, processor free time, stall cycle aggregation, embedded systems, low power, code transformation
1	Jun Zhu, Ingo Sander, Axel Jantsch	Energy efficient streaming applications with guaranteed throughput on MPSoCs.	EMSOFT	2008	DBLP DOI BibTeX RDF	synchronous moc, energy efficiency, mpsocs, streaming applications
1	Lerong Cheng, Yan Lin, Lei He	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA power model, FPGA architecture
1	Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen	Power-efficient and scalable load/store queue design via address compression.	SAC	2008	DBLP DOI BibTeX RDF	address compression, load-store queue, scalable design, power-efficient
1	Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian	Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	cosynthesis, energy, Real-time scheduling, MPSoC
1	Jianli Zhuo, Chaitali Chakrabarti	Energy-efficient dynamic task scheduling algorithms for DVS systems.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	DVS system, Dynamic task scheduling, optimal scaling factor, real time, energy minimization
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation shuffling over cycle boundaries for low energy L0 clustering.	ASAP	2008	DBLP DOI BibTeX RDF
1	Wenjing Yang, Canqun Yang	Exploiting Energy Saving Opportunity of Barrier Operation in MPI Programs.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	MPI, energy saving, barrier
1	Aviral Shrivastava, Ilya Issenin, Nikil Dutt	A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	P. Lopes dos Santos, José A. Ramos, J. L. Martins de Carvalho	Identification of LPV systems using successive approximations.	CDC	2008	DBLP DOI BibTeX RDF
1	Hideaki Kimura, Mitsuhisa Sato, Takayuki Imada, Yoshihiko Hotta	Runtime DVFS control with instrumented Code in power-scalable cluster system.	CLUSTER	2008	DBLP DOI BibTeX RDF
1	Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue	Improved Policies for Drowsy Caches in Embedded Processors.	DELTA	2008	DBLP DOI BibTeX RDF	Low Power Cache Design, Leakage Energy, Drowsy Cache
1	Qiaoyan Yu, Paul Ampadu	Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.	DFT	2008	DBLP DOI BibTeX RDF
1	Meikang Qiu, Jiande Wu, Jingtong Hu, Yi He, Edwin Hsing-Mean Sha	Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment.	EUC	2008	DBLP DOI BibTeX RDF
1	Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara	A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems.	EUC	2008	DBLP DOI BibTeX RDF
1	Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte	Energy-aware opcode design.	ICCD	2008	DBLP DOI BibTeX RDF
1	Pieter De Mil, Tim Allemeersch, Ingrid Moerman, Piet Demeester, Wim De Kimpe	A Scalable Low-Power WSAN Solution for Large-Scale Building Automation.	ICC	2008	DBLP DOI BibTeX RDF
1	Andres Mejia, Jose Flich, José Duato	On the Potentials of Segment-Based Routing for NoCs.	ICPP	2008	DBLP DOI BibTeX RDF
1	Seungyong Oh, Jungsoo Kim, Seonpil Kim, Chong-Min Kyung	Task partitioning algorithm for intra-task dynamic voltage scaling.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen	Address compression for scalable load/store queue implementation.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Ricky Yiu-kee Choi, Chi-Ying Tsui	A Low Energy Two-Step Successive Approximation Algorithm for ADC Design.	ISQED	2008	DBLP DOI BibTeX RDF	Successive Approximation Register ADC, Low Power
1	Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner	Reconfigurable energy efficient near threshold cache architectures.	MICRO	2008	DBLP DOI BibTeX RDF
1	Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang	Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	interconnnection, reliability, low power, network-on-chip
1	Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li	Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng	Energy-Aware Flash Memory Management in Virtual Memory System.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF