Search results for "Enhanced scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Seongmoon Wang, Wenlong Wei	Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns.	European Test Symposium	2008	DBLP DOI BibTeX RDF	Transition delay fault, broadside, skewed-load, enhanced scan
2	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
2	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Anzhela Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh	Selection of the state variables for partial enhanced scan techniques.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Takashi Ikeda, Hideo Ito	Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Songwei Pei, Huawei Li, Xiaowei Li	Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan.	PRDC	2009	DBLP DOI BibTeX RDF
1	K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh	Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri	A robust pulsed flip-flop and its use in enhanced scan design.	ICCD	2009	DBLP DOI BibTeX RDF
1	Zhen Chen, Boxue Yin, Dong Xiang	Conflict driven scan chain configuration for high transition fault coverage and low test power.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Boxue Yin, Dong Xiang, Zhen Chen	New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li	Layout-aware scan chain reorder for launch-off-shift transition test coverage.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	scan chain ordering, test generation, transition faults, Scan test
1	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Takashi Ikeda, Kazuteru Namba, Hideo Ito	Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.	DFT	2007	DBLP DOI BibTeX RDF
1	Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.	DFT	2007	DBLP DOI BibTeX RDF
1	Kedarnath J. Balakrishnan, Lei Fang	RTL Test Point Insertion to Reduce Delay Test Volume.	VTS	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.	DFT	2006	DBLP DOI BibTeX RDF
1	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz	On test generation for transition faults with minimized peak power dissipation.	DAC	2004	DBLP DOI BibTeX RDF	test generation, power dissipation, transition faults
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.	ITC	2004	DBLP DOI BibTeX RDF
1	Arun Krishnamachary, Jacob A. Abraham	Effects of Multi-cycle Sensitization on Delay Tests.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota	Development of Energy Consumption Ratio Test.	VTS	2003	DBLP DOI BibTeX RDF
1	Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara	Design for Two-Pattern Testability of Controller-Data Path Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Jose Miguel Vieira dos Santos	Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells.	IOLTW	2002	DBLP DOI BibTeX RDF	Sequential logic, Dependability, DFT, BST
1	Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa	A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits.	VTS	2002	DBLP DOI BibTeX RDF
1	Seongmoon Wang, Sandeep K. Gupta	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara	Design for Hierarchical Two-Pattern Testability of Data Paths.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Ramesh C. Tekumalla, Premachandran R. Menon	Delay Testing with Clock Control: An Alternative to Enhanced Scan.	ITC	1997	DBLP DOI BibTeX RDF
1	Ramesh C. Tekumalla, Premachandran R. Menon	Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.	ICCD	1997	DBLP BibTeX RDF
1	Sandeep Bhatia, Niraj K. Jha	Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
1	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits.	ITC	1991	DBLP DOI BibTeX RDF