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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 48 occurrences of 40 keywords
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Results
Found 30 publication records. Showing 30 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Cristina Barrado, Roc Messeguer, Juan López, Enric Pastor, Eduard Santamaria, Pablo Royo |
Wildfire Monitoring Using a Mixed Air-Ground Mobile Network.  |
IEEE Pervasive Computing  |
2010 |
DBLP DOI BibTeX RDF |
mobile ad hoc network, pervasive computing, mobile applications, Wi-Fi, firefighting, UAS |
| 1 | Esther Salamí, Sol Pedre, Patricia Borensztejn, Cristina Barrado, Andres Stoliar, Enric Pastor |
Decision Support System for Hot Spot Detection.  |
Intelligent Environments  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Manitra Rakotoarisoa, Enric Pastor |
BMC Encoding for Concurrent Systems.  |
SCCC  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan López, Pablo Royo, Enric Pastor, Cristina Barrado, Eduard Santamaria |
A middleware architecture for unmanned aircraft avionics.  |
Middleware (Demos and Posters)  |
2007 |
DBLP DOI BibTeX RDF |
service-based, middleware, implementation, embedded, UAV, publish-subscribe, avionics |
| 1 | Enric Pastor, Juan López, Pablo Royo |
An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles.  |
DSD  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Marco A. Peña, Marc Solé |
TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems.  |
CAV  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Marc Solé, Enric Pastor |
Evaluating Symbolic Traversal Algorithms Applied to Asynchronous Concurrent Systems.  |
ACSD  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Marco A. Peña |
Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems.  |
CHARME  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Marco A. Peña |
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems.  |
DATE  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Josep Carmona, Jordi Cortadella, Enric Pastor |
A structural encoding technique for the synthesis of asynchronous circuits.  |
Fundam. Inform.  |
2002 |
DBLP BibTeX RDF |
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| 1 | Marc Solé, Enric Pastor |
Traversal Techniques for Concurrent Systems.  |
FMCAD  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Marco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor |
A Case Study for the Verification of Complex Timed Circuits: IPCMOS.  |
DATE  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Josep Carmona, Jordi Cortadella, Enric Pastor |
Synthesis of Reactive Systems: Application to Asynchronous Circuit Design.  |
Concurrency and Hardware Design  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Jordi Cortadella, Oriol Roig |
Symbolic Analysis of Bounded Petri Nets.  |
IEEE Trans. Computers  |
2001 |
DBLP DOI BibTeX RDF |
Binary Decition Diagrams, Petri nets, formal verification, symbolic methods |
| 1 | Josep Carmona, Jordi Cortadella, Enric Pastor |
A structural encoding technique for the synthesis of asynchronous circuits.  |
ACSD  |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev |
Formal Verification of Safety Properties in Timed Circuits. (PDF / PS)  |
ASYNC  |
2000 |
DBLP DOI BibTeX RDF |
Formal verification, asynchronous circuits, timing analysis |
| 1 | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev |
Decomposition and technology mapping of speed-independent circuits using Boolean relations.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Jordi Cortadella, Marco A. Peña |
Structural Methods to Improve the Symbolic Analysis of Petri Nets.  |
ICATPN  |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig |
Structural methods for the synthesis of speed-independent circuits.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Jordi Cortadella |
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets.  |
DATE  |
1998 |
DBLP DOI BibTeX RDF |
Petri nets, BDDs, symbolic analysis |
| 1 | Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno |
Partial order based approach to synthesis of speed-independent circuits.  |
ASYNC  |
1997 |
DBLP DOI BibTeX RDF |
approximation, synthesis, asynchronous circuits, unfolding, Signal Transition Graph |
| 1 | Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella |
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment.  |
DAC  |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Oriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor |
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits.  |
DAC  |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev |
Decomposition and technology mapping of speed-independent circuits using Boolean relations.  |
ICCAD  |
1997 |
DBLP DOI BibTeX RDF |
Boolean decomposition, decomposed logic sharing, design library, library matching, logic decomposition, logic resynthesis, signal insertion, two-input combinational gate, two-input sequential gate, optimization, technology mapping, circuit CAD, speed-independent circuits, netlist, complex gates, Boolean relations |
| 1 | Oriol Roig, Jordi Cortadella, Enric Pastor |
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets.  |
Application and Theory of Petri Nets  |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Enric Pastor, Jordi Cortadella, Oriol Roig |
A new look at the conditions for the synthesis of speed-independent circuits.  |
Great Lakes Symposium on VLSI  |
1995 |
DBLP DOI BibTeX RDF |
gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits |
| 1 | Oriol Roig, Jordi Cortadella, Enric Pastor |
Hierarchical gate-level verification of speed-independent circuits.  |
ASYNC  |
1995 |
DBLP DOI BibTeX RDF |
hierarchical gate-level verification, state signals, computational complexity, logic testing, time complexity, asynchronous circuits, speed-independent circuits, complex gates |
| 1 | Enric Pastor, Oriol Roig, Jordi Cortadella, Rosa M. Badia |
Petri Net Analysis Using Boolean Manipulation.  |
Application and Theory of Petri Nets  |
1994 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Jordi Cortadella |
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs.  |
ICCAD  |
1993 |
DBLP DOI BibTeX RDF |
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| 1 | Enric Pastor, Jordi Cortadella |
An Efficient Unique State Coding Algorithm for Signal Transition Graphs.  |
ICCD  |
1993 |
DBLP BibTeX RDF |
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