Search results for "Enrico Macii"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andrea Calimera, Enrico Macii, Massimo Poncino	Design Techniques for NBTI-Tolerant Power-Gating Architectures.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI effects on tree-like clock distribution networks.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Haroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii	Application-specific memory partitioning for joint energy and lifetime optimization.	DATE	2012	DBLP BibTeX RDF
1	Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Rich Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo	Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.	DATE	2012	DBLP BibTeX RDF
1	Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino	IR-drop analysis of graphene-based power distribution networks.	DATE	2012	DBLP BibTeX RDF
1	Edoardo Patti, Andrea Acquaviva, Francesco Abate, Anna Osello, A. Cocuccio, Marco Jahn, Marc Jentsch, Enrico Macii	Middleware services for network interoperability in smart energy efficient buildings.	DATE	2012	DBLP BibTeX RDF
1	Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii	A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Paula Helena Reyes-Herrera, Elisa Ficarra, Andrea Acquaviva, Enrico Macii	miREE: miRNA Recognition Elements Ensemble.	BMC Bioinformatics	2011	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Buffering of frequent accesses for reduced cache aging.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Francesco Abate, Andrea Acquaviva, Elisa Ficarra, Giulia Paciello, Enrico Macii, Alberto Ferrarini, Massimo Delledonne, Simona Soverini, Giovanni Martinelli	A novel framework for chimeric transcript detection based on accurate gene fusion model.	BIBM Workshops	2011	DBLP DOI BibTeX RDF
1	Santa Di Cataldo, Elisa Ficarra, Andrea Acquaviva, Enrico Macii	Motion Artifact Correction in ASL images: An Improved Automated Procedure.	BIBM	2011	DBLP DOI BibTeX RDF
1	Francesco Abate, Andrea Acquaviva, Elisa Ficarra, Enrico Macii	A New Latent Semantic Analysis based Methodology for Knowledge Extraction from Biomedical Literature and Biological Pathways Databases.	BIOINFORMATICS	2011	DBLP BibTeX RDF
1	Giulia Paciello, Andrea Acquaviva, Elisa Ficarra, M. A. Deriu, A. Grosso, Enrico Macii	Binding Free Energy Calculation via Molecular Dynamics Simulations for a miRNA: mRNA Interaction.	BIOINFORMATICS	2011	DBLP BibTeX RDF
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Partitioned cache architectures for reduced NBTI-induced aging.	DATE	2011	DBLP DOI BibTeX RDF
1	Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino	A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino	Dual-Vt assignment policies in ITD-aware synthesis.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-Aware Clustered Power Gating.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Mirko Loghi, Olga Golubeva, Enrico Macii, Massimo Poncino	Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	memory hierarchy, leakage power, Power optimization, scratchpad memory, partitioning algorithm, embedded design
1	Santa Di Cataldo, Elisa Ficarra, Andrea Acquaviva, Enrico Macii	Achieving the way for automated segmentation of nuclei in cancer tissue images through morphology-based approach: A quantitative evaluation.	Comp. Med. Imag. and Graph.	2010	DBLP DOI BibTeX RDF
1	Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino	Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Santa Di Cataldo, Elisa Ficarra, Andrea Acquaviva, Enrico Macii	Automated segmentation of tissue images for computerized IHC analysis.	Computer Methods and Programs in Biomedicine	2010	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	David Cuesta, José L. Ayala, José Ignacio Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii	Adaptive Task Migration Policies for Thermal Control in MPSoCs.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Dynamic indexing: concurrent leakage and aging optimization for caches.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage optimization, memory hierarchy, aging, NBTI
1	Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda	Generating power-hungry test programs for power-aware validation of pipelined processors.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii	Power-aware partitioning of data converters.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Aging effects of leakage optimizations for caches.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	memory hierarchy, aging, leakage reduction
1	Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella	An integrated thermal estimation framework for industrial embedded platforms.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	system-on-chip, power, estimation, thermal
1	David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii	Thermal-aware floorplanning exploration for 3D multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	3D, floorplanning, MPSoC, temperature
1	Francesco Abate, Elisa Ficarra, Andrea Acquaviva, Enrico Macii	An Automated Tool for Scoring Biomedical Terms Correlation Based on Semantic Analysis.	CISIS	2010	DBLP DOI BibTeX RDF	ontologies, text-mining, thesaurus, Gene Ontology
1	Paula Helena Reyes-Herrera, Andrea Acquaviva, Elisa Ficarra, Enrico Macii	MicroRNA Target Prediction and Exploration through Candidate Binding Sites Generation.	CISIS	2010	DBLP DOI BibTeX RDF	microRNA target prediction, Genetic Algorithm, motifs
1	Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino	Post-placement temperature reduction techniques.	DATE	2010	DBLP BibTeX RDF
1	Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Piero Perlo, Andreas Wild, Roberto Zafalon	Panel: First commandment at least, do nothing well!	DATE	2010	DBLP BibTeX RDF
1	Andrea Calimera, Enrico Macii, Massimo Poncino	Analysis of NBTI-induced SNM degradation in power-gated SRAM cells.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Prassanna Sithambaram, Alberto Macii, Enrico Macii	Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.	J. Embedded Computing	2009	DBLP DOI BibTeX RDF
1	Enrico Macii	Editorial.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino	Data-Driven Clock Gating for Digital Filters.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino	On-chip Thermal Modeling Based on SPICE Simulation.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware power gating for concurrent leakage and aging optimization.	ISLPED	2009	DBLP DOI BibTeX RDF	aging, leakage, power-gating, nbti
1	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware sleep transistor design for reliable power-gating.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, sizing, sleep-transistor, nbti
1	Karthik Duraisami, Enrico Macii, Massimo Poncino	Using soft-edge flip-flops to compensate NBTI-induced delay degradation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	device aging, seff, setup and hold time, flip-flop, circuit reliability, nbti
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii	Physically clustered forward body biasing for variability compensation in nanometer CMOS design.	DATE	2009	DBLP BibTeX RDF
1	Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	Enabling concurrent clock and power gating in an industrial design flow.	DATE	2009	DBLP BibTeX RDF
1	Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	Placement-aware Clustering for Integrated Clock and Power Gating.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal-Aware Design Techniques for Nanometer CMOS Circuits.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Enrico Macii	Editorial.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Elisa Ficarra, Giovanni De Micheli, Sungroh Yoon, Luca Benini, Enrico Macii	Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.	Computers & Mathematics with Applications	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.	Integration	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino	Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar	Temperature-insensitive synthesis using multi-vt libraries.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	multi-threshold voltage, temperature-aware, logic synthesis
1	Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja (eds.)	Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008	ACM Great Lakes Symposium on VLSI	2008	DBLP BibTeX RDF
1	Karthik Duraisami, Enrico Macii, Massimo Poncino	Energy efficiency bounds of pulse-encoded buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	power reduction., pulse wave transmission, high-speed interconnect, transition activity
1	Santa Di Cataldo, Elisa Ficarra, Andrea Acquaviva, Enrico Macii	Segmentation of nuclei in cancer tissue images: Contrasting active contours with morphology-based approach.	BIBE	2008	DBLP DOI BibTeX RDF
1	Santa Di Cataldo, Elisa Ficarra, Enrico Macii	Automated Discrimination of Pathological Regions in Tissue Images: Unsupervised Clustering vs. Supervised SVM Classification.	BIOSTEC (Selected Papers)	2008	DBLP DOI BibTeX RDF	Tissue segmentation, tissue confocal images, immunohistochemistry, Support Vector Machine, K-means clustering
1	Santa Di Cataldo, Elisa Ficarra, Enrico Macii	Fully-Automated Segmentation of Tumor Areas in Tissue Confocal Images - Comparison between a Custom Unsupervised and a Supervised SVM Approach.	BIOSIGNALS	2008	DBLP BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	A Scalable Algorithmic Framework for Row-Based Power-Gating.	DATE	2008	DBLP DOI BibTeX RDF
1	Andrea Calimera, Luca Benini, Enrico Macii	Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.	DATE	2008	DBLP DOI BibTeX RDF
1	Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii	Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.	DATE	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Enrico Macii	Editorial.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar	In Memoriam: Margarida F. Jacome.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Prassanna Sithambaram, Alberto Macii, Enrico Macii	New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Simone Medardoni, Davide Bertozzi, Enrico Macii	Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	RTL synthesis, leakage-aware, power management, selection strategy
1	Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino	Locality-driven architectural cache sub-banking for leakage energy reduction.	ISLPED	2007	DBLP DOI BibTeX RDF	banked cache, memory hierarchy, leakage reduction, architectural optimization
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud (eds.)	Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007	ACM Great Lakes Symposium on VLSI	2007	DBLP BibTeX RDF
1	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
1	Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis	Early Power-Aware Design & Validation: Myth or Reality?	DAC	2007	DBLP DOI BibTeX RDF
1	Elena Baralis, Elisa Ficarra, Alessandro Fiori, Enrico Macii	Gene-Markers Representation for Microarray Data Integration.	BIBE	2007	DBLP DOI BibTeX RDF
1	Santa Di Cataldo, Elisa Ficarra, Enrico Macii	Selection of Tumor Areas and Segmentation of Nuclear Membranes in Tissue Confocal Images: A Fully Automated Approach.	BIBM	2007	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.	DATE	2007	DBLP DOI BibTeX RDF
1	Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii	Architectural leakage-aware management of partitioned scratchpad memories.	DATE	2007	DBLP DOI BibTeX RDF
1	Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino	Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon	Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini	Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini	Optimized Technique for Dna Structural Properties Discovering.	International Journal on Artificial Intelligence Tools	2006	DBLP DOI BibTeX RDF
1	Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino	Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Simona Rossi, Daniele Masotti, Christine Nardini, Elena Bonora, Giovanni Romeo, Enrico Macii, Luca Benini, Stefano Volinia	TOM: a web-based integrated approach for identification of candidate disease genes.	Nucleic Acids Research	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
1	Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino	STV-Cache: a leakage energy-efficient architecture for data caches.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	architecture, caches, leakage power
1	Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini	Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.	CBMS	2006	DBLP DOI BibTeX RDF
1	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Enabling fine-grain leakage management by voltage anchor insertion.	DATE	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino	Thermal resilient bounded-skew clock tree optimization methodology.	DATE	2006	DBLP DOI BibTeX RDF
1	Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon	Low-power design tools: are EDA vendors taking this matter seriously?	DATE	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	A. Nurrachmat, Enrico Macii, Massimo Poncino	Low-energy pixel approximation for DVI-based LCD interfaces.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini	Mining Gene Sets for Measuring Similarities.	ISCC	2006	DBLP DOI BibTeX RDF

Publications of "Enrico Macii" ( http://dblp.L3S.de/Authors/Enrico_Macii )