| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | M. Zhang, R. Haussler, Markus Olbrich, Harald Kinzelbach, Erich Barke |
A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization.  |
VLSI Design  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz |
A gate sizing method for glitch power reduction. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz |
A theoretical probabilistic simulation framework for dynamic power estimation. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke |
Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann |
An Accelerated Mixed-Signal Simulation Kernel for SystemC. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke |
Towards Abstract Analysis Techniques for Range Based System Simulations. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang |
Formal approaches to analog circuit verification. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler |
Fast dynamic power estimation considering glitch filtering. |
SoCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl |
Considering possible opens in non-tree topology wire delay calculation. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
non-tree topologies, yield, static timing analysis, delay analysis |
| 1 | Darius Grabowski, Markus Olbrich, Erich Barke |
Analog circuit simulation using range arithmetics. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Olbrich, Erich Barke |
Distribution arithmetic for stochastical analysis. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt |
Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). |
FDL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Leppelt, Erich Barke |
Determining the Technical Complexity of Integrated Circuits. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke |
A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Torben Weinkopf, Klaus Harbich, Erich Barke |
Incremental Fault Emulation. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl |
Robust wiring networks for DfY considering timing constraints. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
redundant wiring, timing constraint aware, open defects, design for yield |
| 1 | Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten |
Algorithms for automatic length compensation of busses in analog integrated circuits. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
analog routing, length compensation, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout |
| 1 | Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke |
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke |
Range Arithmetics to Speed up Reachability Analysis of Analog Systems. |
FDL |
2007 |
DBLP BibTeX RDF |
|
| 1 | M. Zhang, Markus Olbrich, D. Seider, M. Frerichs, Harald Kinzelbach, Erich Barke |
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke |
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. |
Electr. Notes Theor. Comput. Sci. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Torben Weinkopf, Klaus Harbich, Erich Barke |
Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Platte, S. Jing, R. Sommer, Erich Barke |
Using Sequential Equations to Improve Efficiency and Robustness. |
FDL |
2006 |
DBLP BibTeX RDF |
|
| 1 | Darius Grabowski, Christoph Grimm, Erich Barke |
Semi-symbolic modeling and simulation of circuits and systems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten |
Routing of analog busses with parasitic symmetry. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout |
| 1 | Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke |
Wirelength Reduction Using 3-D Physical Design. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Olbrich, Erich Barke |
Placement Using a Localization Probability Model (LPM). (PDF / PS) |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke |
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Hermann, Markus Olbrich, Erich Barke |
Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. |
VLSI-SOC |
2003 |
DBLP BibTeX RDF |
|
| 1 | Walter Hartong, Lars Hedrich, Erich Barke |
Model checking algorithms for analog verification. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
nonlinear analog systems, model checking, formal methods |
| 1 | Silke Salewski, Erich Barke |
An Upper Bound for 3D Slicing Floorplans. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke |
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Joerg Abke, Erich Barke |
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Walter Hartong, Lars Hedrich, Erich Barke |
An Approach to Model Checking for Nonlinear Analog Systems. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Walter Hartong, Lars Hedrich, Erich Barke |
On Discrete Modeling and Model Checking for Nonlinear Analog Systems. |
CAV |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas C. Lemke, Lars Hedrich, Erich Barke |
Analog circuit sizing based on formal methods using affine arithmetic. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch |
CHIPDESIGN - A Novel Project-oriented Microelectronics Course. (PDF / PS) |
MSE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Joerg Abke, Erich Barke |
A New Placement Method for Direct Mapping into LUT-Based FPGAs. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Klaus Harbich, Erich Barke |
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Joachim Küter, Erich Barke |
Architecture driven partitioning. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Olbrich, Achim Rein, Erich Barke |
An improved hierarchical classification algorithm for structural analysis of integrated circuits. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Joerg Abke, Erich Barke |
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Soudris, Peter Pirsch, Erich Barke (eds.) |
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings |
PATMOS |
2000 |
DBLP BibTeX RDF |
|
| 1 | Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel |
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke |
A current driven routing and verification methodology for analog applications. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
multiterminal signal nets, routing, verification, design methodology, Steiner tree, electromigration, current density |
| 1 | Thorsten Adler, Erich Barke |
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthias Ringe, Thomas Lindenkreuz, Erich Barke |
Static Timing Analysis Taking Crosstalk into Account. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Joerg Abke, Erich Barke, Jörn Stohmann |
A Universal Module Generator for LUT-Based FPGAs. (PDF / PS) |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
Multiplexor, Multiplexor Structure, FPGA, Technology Mapping, Module Generator |
| 1 | Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer |
A Case Study: Logic Emulation - Pitfalls and Solutions. (PDF / PS) |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
Evaluation Mentor Graphics Corporation, SimExpress, Quickturn Design Systems, Inc., System Realizer, Rapid Prototyping, Logic Emulation |
| 1 | Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke |
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Reza Sedaghat-Maman, Erich Barke |
Real Time Fault Injection Using Logic Emulators. |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Matthias Ringe, Thomas Lindenkreuz, Erich Barke |
Path Verification Using Boolean Satisfiability. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
False Path Problem, Dynamic Esperance, Satisfiability, Static Timing Analysis |
| 1 | Lars Hedrich, Erich Barke |
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
electronic design automation circuit simulation, formal verification, analog circuits |
| 1 | Jörn Stohmann, Erich Barke |
A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. |
ICCD |
1997 |
DBLP BibTeX RDF |
|
| 1 | Jörn Stohmann, Erich Barke |
A Universal CLA Adder Generator for SRAM-Based FPGAs. |
FPL |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Carsten Borchers, Lars Hedrich, Erich Barke |
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Dirk Behrens, Klaus Harbich, Erich Barke |
Hierarchical partitioning. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Clustering, FPGAs, Partitioning, Logic Emulation, Design Hierarchy |
| 1 | Lars Hedrich, Erich Barke |
A formal approach to nonlinear analog circuit verification. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
analog nonlinear circuits, formal verification, functional verification, electronic design automation, behavioral description |
| 1 | Erich Barke |
Line-to-ground capacitance calculation for VLSI: a comparison. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1988 |
DBLP DOI BibTeX RDF |
|
| 1 | Erich Barke |
FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. |
Angewandte Informatik |
1985 |
DBLP BibTeX RDF |
|
| 1 | Erich Barke |
Resistance calculation from mask artwork data by finite element method. |
DAC |
1985 |
DBLP DOI BibTeX RDF |
|
| 1 | F. Luellau, T. Hoepken, Erich Barke |
A technology independent block extraction algorithm. |
DAC |
1984 |
DBLP BibTeX RDF |
|
| 1 | Erich Barke |
A layout verification system for analog bipolar integrated circuits. |
DAC |
1983 |
DBLP BibTeX RDF |
|
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