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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Valeria Garofalo, Nicola Petra, Ettore Napoli |
Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error.  |
IEEE Trans. Computers  |
2011 |
DBLP DOI BibTeX RDF |
truncated multipliers, maximum error, digital arithmetic, error analysis, Multiplication, error compensation |
| 1 | Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo |
Design of Fixed-Width Multipliers With Linear Compensation Function. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Nicola Petra, Davide De Caro, Valeria Garofalo, Ettore Napoli, Antonio G. M. Strollo |
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Valeria Garofalo, Marino Coppola, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo |
A novel truncated squarer with linear compensation function. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Davide De Caro, Marino Coppola, Nicola Petra, Ettore Napoli, Antonio G. M. Strollo, Valeria Garofalo |
High-speed differential resistor ladder for A/D converters. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Nicola Petra, Davide De Caro, Antonio G. M. Strollo, Valeria Garofalo, Ettore Napoli, Marino Coppola, Pietro Todisco |
Fixed-width CSD multipliers with minimum mean square error. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra |
A novel high-speed sense-amplifier-based flip-flop. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio G. M. Strollo, Ettore Napoli, C. Cimino |
Analysis of power dissipation in double edge-triggered flip-flops. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Antonio G. M. Strollo, Ettore Napoli, Davide De Caro |
New clock-gating techniques for low-power flip-flops. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits |
Displaying result #1 - #9 of 9 (100 per page; Change: )
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