Search results for "European Test Symposium"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre	Scan Attacks and Countermeasures in Presence of Scan Response Compactors.	European Test Symposium	2011	DBLP DOI BibTeX RDF	scan-based attack, security, testability, response compaction
1	Min Li, Michael S. Hsiao	High-Performance Diagnostic Fault Simulation on GPUs.	European Test Symposium	2011	DBLP DOI BibTeX RDF	diagnostic faut simulation, general-purpose computing on graphics processing unit (GPGPU), parallel algorithm, compute unified device architecture (CUDA)
1	Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein	Structural In-Field Diagnosis for Random Logic Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	In-field diagnosis, Built-In Self-Diagnosis
1	Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara	Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo, L. Perilli, Roberto Cardu, Eleonora Franchi, C. Gozzi, F. Maggioni	Input/Output Pad for Direct Contact and Contactless Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	wireless probing, I/O, SiP, capacitive coupling
1	Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai	A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.	European Test Symposium	2011	DBLP DOI BibTeX RDF	3-D IC testing, calibration-oriented testing, pre-, post-bond testing, SAR ADC, mixed-signal testing
1	Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita	Optimization of Assertion Placement in Time-Constrained Embedded Systems.	European Test Symposium	2011	DBLP DOI BibTeX RDF	time-constrained embedded systems, soft errors, executable assertions
1	Shaji Krishnan, Hans G. Kerkhoff	A Robust Metric for Screening Outliers from Analogue Product Manufacturing Tests Responses.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Analogue, Reliability, Test, Outliers, Mahalanobis distance
1	Stelios Neophytou, Kyriakos Christou, Maria K. Michael	An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration.	European Test Symposium	2011	DBLP DOI BibTeX RDF	zero-supressed binary decision diagrams, digital circuits, path similarity
1	Ramachandran Venkatasubramanian, Doohwang Chang, Sule Ozev	Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case Study.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Rick Wong, Shi-Jie Wen	Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	AVF Analysis Acceleration via Hierarchical Fault Pruning.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui	Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.	European Test Symposium	2011	DBLP DOI BibTeX RDF	3D stacked-IC, memory redundancy, 3D memory, yield enhancement
1	Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor	Critical Fault-Based Pattern Generation for Screening SDDs.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Afsaneh Nassery, Sule Ozev, Marian Verhelst, Mustapha Slamani	Extraction of EVM from Transmitter System Parameters.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Dongsoo Lee, Kaushik Roy	Viterbi-Based Efficient Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	On-Chip Decompressor, Scalability, Logic Test, Test Data Compression, Low-Power Test
1	Sandra Irobi, Zaid Al-Ars, Said Hamdioui	Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Parasitic Bit Line coupling, SRAMs, Memory tests
1	Yukiya Miura	Dual Edge Triggered Flip-Flops for Noise Aware Design.	European Test Symposium	2011	DBLP DOI BibTeX RDF	data signal, dependable design, edge triggered flip-flop, noise, synchronous circuits
1	Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee	Power Aware Post-manufacture Tuning of Analog Nanocircuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer	Reduced ATE Interface for High Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	channel bandwidth management, embedded deterministic test, test interface, tri-modal compression, test data compression, scan-based designs
1	Hongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty	Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell	Towards Variation-Aware Test Methods.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Delay test, Adaptive test, Parameter variations
1		16th European Test Symposium (ETS 2011), May 23-27, 2011, Trondheim, Norway	European Test Symposium	2011	DBLP BibTeX RDF
1	Masoud Zamani, Navid Farazmand, Mehdi Baradaran Tahoori	Fault Masking and Diagnosis in Reversible Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Majority voter, Reversible logic, Fault masking
1	Alessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca	Revisiting Application-Dependent Test for FPGA Devices.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Application-Dependent test, FPGA test
1	Anelise Kologeski, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt	Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Data Splitting, Fault Tolerance, Mapping, Adaptive Routing, Links, NoCs
1	Michael Nicolaidis, Vladimir Pasca, Lorena Anghel	I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar	Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis.	European Test Symposium	2011	DBLP DOI BibTeX RDF	on-chip diagnosis, test set selection, Logic Implications
1	Dhiego Silva, K. Stangherlin, Leticia Maria Veiras Bolzani, Fabian Vargas	A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Hardware-Based Approach, RTOS
1	Esa Korhonen, Juha Kostamovaara	Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs.	European Test Symposium	2011	DBLP DOI BibTeX RDF	didital-analog conversion, algorithms, testing, histograms, linearity, analog-digital conversion
1	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.	European Test Symposium	2011	DBLP DOI BibTeX RDF	RTL fault simulation, fault simulation acceleration, RTL-to-TLM abstraction
1	Ioannis Voyiatzis, Costas Efstathiou, H. Antonopoulou	A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu	DfT Architecture for 3D-SICs with Multiple Towers.	European Test Symposium	2011	DBLP DOI BibTeX RDF	three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via
1	Uros Legat, Anton Biasizzo, Franc Novak	FPGA Soft Error Recovery Mechanism with Small Hardware Overhead.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu	Toggle-Based Masking Scheme for Clustered Unknown Response Bits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	response unknowns, unknown masking, scan based test, response compaction
1	Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer	Diagnosis of Failing Scan Cells through Orthogonal Response Compaction.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Enhancement of Clock Delay Faults Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Clock line, Test Generation, Delay faults
1	Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini	A Low-Cost Emulation System for Fast Co-verification and Debug.	European Test Symposium	2011	DBLP DOI BibTeX RDF	FPGA, debug, System-on-Chip, co-verification
1	Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes	Tomographic Testing and Validation of Probabilistic Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Probabilistic testing, quantum computing
1	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	European Test Symposium	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
1	Stephen K. Sunter, Aubin Roy	A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution.	European Test Symposium	2011	DBLP DOI BibTeX RDF	mixed-signal DFT, analog bus, mixed-signal BIST
1	Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty	Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Multi-Mode Power Switches, DFT for Multicore Chips, Static Power Management, Testing, Voltage-Control Oscillator
1	Ender Yilmaz, Sule Ozev	Fast and Accurate DPPM Computation Using Model Based Filtering.	European Test Symposium	2011	DBLP DOI BibTeX RDF	DPPM, Analog/Mixed Signal, Simulation, Importance sampling, Test Quality
1	Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich	Structural Test for Graceful Degradation of NoC Switches.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Logic Diagnosis, Performability, Network-on-Chip, Graceful Degradation
1	S. Kook, A. Banerjee, Abhijit Chatterjee	Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Feng Yuan, Xiao Liu, Qiang Xu	On High-Quality Test Pattern Selection and Manipulation.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Pseudo-functional testing, test overkill, test escape, test pattern selection
1	H. C. M. Bossers, Johann Hurink, Gerard J. M. Smit	Online Univariate Outlier Detection in Final Test: A Robust Rolling Horizon Approach.	European Test Symposium	2011	DBLP DOI BibTeX RDF	online outlier detection, final test, robust
1	S. Saqib Khursheed, Sheng Yang, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn	Improved DFT for Testing Power Switches.	European Test Symposium	2011	DBLP DOI BibTeX RDF	power switch, leakage power management, test time overhead, DFT, design for test, Sleep transistor
1	Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh	Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.	European Test Symposium	2011	DBLP DOI BibTeX RDF	GRAAL, fault detection, DSP, soft error, SETs
1	Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	At-speed delay fault testing, Power-aware Testing, Functional power
1	Irith Pomeranz	On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Broadside tests, multicycle tests, fault diagnosis, transition faults
1	Alexander Finder, André Sülflow, Görschwin Fey	Latency Analysis for Sequential Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Soft Error Analysis, f, Debugging, Sequential Circuits, Latency
1	Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara	Temperature-Variation-Aware Test Pattern Optimization.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue	Hybrid test application in hybrid delay scan design.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Sachin Dileep Dasnurkar, Jacob A. Abraham	Calibration-enabled scalable built-in current sensor compatible with very low cost ATE.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Johannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner	Fast simulation based testing of anti-tearing mechanisms for small embedded systems.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Masoud Zamani, Mehdi Baradaran Tahoori	A transient error tolerant self-timed asynchronous architecture.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Erik Larsson, Bart Vermeulen, Kees Goossens	A distributed architecture to check global properties for post-silicon debug.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara	Test pattern selection to optimize delay test quality with a limited size of test set.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Yang Jin, Hong Wang, Zhengliang Lv, Shiyuan Yang	Pipelined parallel test structure for mixed-signal SoCs.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Emil Gizdarski	Constructing augmented time compactors.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Michael Campbell	Plenary presentations: Keynote: The product complexity and test - How product complexity impacts test industry.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis	On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer	Diagnosis of failing scan cells through orthogonal response compaction.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh	Modified T-Flip-Flop based scan cell for RAS.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Yu Zhang, Vishwani D. Agrawal	A diagnostic test generation system and a coverage metric.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante	An integrated flow for the design of hardened circuits on SRAM-based FPGAs.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Frank Poehl, Frank Demmerle, Juergen Alt, Hermann Obermeir	Production test challenges for highly integrated mobile phone SOCs - A case study.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Setting test conditions for improving SRAM reliability.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Shaji Krishnan, Hans G. Kerkhoff	Multivariate model for test response analysis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Jose Luis Garcia-Gervacio, Víctor H. Champac	Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Xiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff	Predicting dynamic specifications of ADCs with a low-quality digital input signal.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Michelangelo Grosso, Wilson J. H. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, J. Velasco Medina	A software-based self-test methodology for system peripherals.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler	Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1		15th European Test Symposium (ETS 2010), May 24-28, 2010, Prague, Czech Republic	European Test Symposium	2010	DBLP BibTeX RDF
1	Ke Peng, Yu Huang 0005, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor	Full-circuit SPICE simulation based validation of dynamic delay estimation.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree	Test-architecture optimization for TSV-based 3D stacked ICs.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Paula Herber, Marcel Pockrandt, Sabine Glesner	Automated conformance evaluation of SystemC designs using timed automata.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Ho Fai Ko, Nicola Nicolici	Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Navid Farazmand, Mehdi Baradaran Tahoori	Multiple fault diagnosis in crossbar nano-architectures.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu	Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Input test data volume reduction based on test vector chains.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas	Low-cost signature test of RF blocks based on envelope response analysis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir	On the use of standard digital ATE for the analysis of RF signals.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita	Current-based testable design of level shifters in liquid crystal display drivers.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla	Add-on blocks and algorithms for improving stimulus compression.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Z. Xu, Andrew Richardson, L. Li, M. Begbie, D. Koltsov, C. H. Wang	A multi-mode MEMS sensor design to support system test and health & usage monitoring applications.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li	A low-cost built-in self-test scheme for an array of memories.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras	Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin	Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee	Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich	Design and implementation of Automatic Test Equipment IP module.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz	Scan based speed-path debug for a microprocessor.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Román Mozuelos, Yolanda Lechuga, Mar Martínez, Salvador Bracho	Test of embedded analog circuits based on a built-in current sensor.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara	Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Gabriel de M. Borges, Luiz Fernando Gonçalves, Tiago R. Balen, Marcelo Lubaszewski	Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda	An adaptive tester architecture for volume diagnosis.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese	Microprocessor fault-tolerance via on-the-fly partial reconfiguration.	European Test Symposium	2010	DBLP DOI BibTeX RDF

Publications at "European Test Symposium"( http://dblp.L3S.de/Venues/European_Test_Symposium )