| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Mario K. Y. Leung, Eric K. I. Chio, Evangeline F. Y. Young |
Postplacement Voltage Island Generation.  |
ACM Trans. Design Autom. Electr. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze |
Postgrid Clock Routing for High Performance Microprocessor Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young |
Crosslink insertion for variation-driven clock network construction. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zigang Xiao, Evangeline F. Y. Young |
Placement and Routing for Cross-Referencing Digital Microfluidic Biochips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young |
Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Huang, Liang Li, Evangeline F. Y. Young |
On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou |
MSV-Driven Floorplanning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham |
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze |
Grid-to-ports clock routing for high performance microprocessor designs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Huang, Evangeline F. Y. Young |
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Evangeline F. Y. Young, Martin D. F. Wong |
An optimal algorithm for layer assignment of bus escape routing on PCBs. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young |
A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong |
A monte-carlo floating-point unit for self-validating arithmetic. |
FPGA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young |
Ripple: An effective routability-driven placer by iterative cell movement. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng |
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Evangeline F. Y. Young |
Multivoltage Floorplan Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Zigang Xiao, Evangeline F. Y. Young |
Droplet-routing-aware module placement for cross-referencing biochips. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
cross-referencing, dmfb, synthesis, placement, microfluidics, biochip |
| 1 | Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng |
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
wire efficiency, bandwidth, power efficiency |
| 1 | Zigang Xiao, Evangeline F. Y. Young |
CrossRouter: a droplet router for cross-referencing digital microfluidic biochips. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young |
A dual-MST approach for clock network synthesis. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young |
Fixed-outline thermal-aware 3D floorplanning. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young |
Local clock skew minimization using blockage-aware mixed tree-mesh clock network. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Huang, Evangeline F. Y. Young |
Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Linfu Xiao, Evangeline F. Y. Young, Xiaoyong He, K. P. Pun |
Practical placement and routing techniques for analog circuit designs. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu |
Congestion prediction in early stages of physical design. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
placement, Estimation, floorplanning |
| 1 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
Handling routability in floorplan design with twin binary trees. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Block flipping and white space distribution for wirelength minimization. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Zaichen Qian, Evangeline F. Y. Young |
Multi-voltage floorplan design with optimal voltage assignment. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
multi-voltage assignment optimization branch-and-bound |
| 1 | Linfu Xiao, Evangeline F. Y. Young |
Analog placement with common centroid and 1-D symmetry constraints. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Li, Zaichen Qian, Evangeline F. Y. Young |
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou |
Optimizing wirelength and routability by searching alternative packings in floorplanning. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
wirelength reduction, Floorplanning |
| 1 | Jill H. Y. Law, Evangeline F. Y. Young |
Multi-bend bus driven floorplanning. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young |
Slicing Floorplan Orientation. |
Encyclopedia of Algorithms |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng |
3-D floorplanning using labeled tree and dual sequences. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
3-D packing, sequence, labeled tree |
| 1 | Tilen Ma, Evangeline F. Y. Young |
TCG-based multi-bend bus driven floorplanning. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Evangeline F. Y. Young |
Network flow-based power optimization under timing constraints in MSV-driven floorplanning. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Li, Evangeline F. Y. Young |
Obstacle-avoiding rectilinear Steiner tree construction. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Area reduction by deadspace utilization on interconnect optimized floorplan. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
area reduction, Floorplanning |
| 1 | Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu |
Wire Retiming Problem With Net Topology Optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Evangeline F. Y. Young |
Voltage island-driven floorplanning. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Ma 0002, Evangeline F. Y. Young, K. P. Pun |
Analog placement with common centroid constraints. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young |
Test scheduling for built-in self-tested embedded SRAMs with data retention faults. |
IET Computers & Digital Techniques |
2007 |
DBLP BibTeX RDF |
|
| 1 | Royce L. S. Ching, Evangeline F. Y. Young |
Shuttle mask floorplanning with modified alpha-restricted grid. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
multi-project wafers, reticle design |
| 1 | Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching |
Block alignment in 3D floorplan using layered TCG. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
3D floorplanning, block alignment |
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu |
Optimal cell flipping in placement and floorplanning. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
flipping, placement, floorplanning, orientation, wirelength |
| 1 | Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu |
Post-placement voltage island generation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
tree, floorplanning, voltage island |
| 1 | Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu |
Analog placement with symmetry and other placement constraints. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
symmetry constraints, placement, analog circuits, sequence-pair |
| 1 | Qiang Xu, Baosheng Wang, F. Y. Young |
Retention-Aware Test Scheduling for BISTed Embedded SRAMs. |
European Test Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jill H. Y. Law, Evangeline F. Y. Young |
Multi-bend bus driven floorplanning. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
bus planning, floorplanning, VLSI CAD |
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion prediction in early stages. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
placement, floorplanning, interconnect estimation |
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion prediction in floorplanning. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Evangeline F. Y. Young |
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho |
Placement constraints in floorplan design. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Dennis K. Y. Tong, Evangeline F. Y. Young |
Performance-driven register insertion in placement. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
post-retiming, register insertion, placement |
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen |
Twin binary sequences: a nonredundant representation for general nonslicing floorplan. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Kei Mak, Evangeline F. Y. Young |
Temporal logic replication for dynamically reconfigurable FPGA partitioning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Routability-driven floorplanner with buffer block planning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Seung Yuen, Evangeline F. Y. Young |
Slicing floorplan with clustering constraint. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak |
Clustering based acyclic multi-way partitioning. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
multi-way, clustering, CAD, partitioning, acyclic |
| 1 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu |
Retiming with Interconnect and Gate Delay. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Routability driven floorplanner with buffer block planning. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen |
Twin binary sequences: a non-redundant representation for general non-slicing floorplan. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Kei Mak, Evangeline F. Y. Young |
Temporal logic replication for dynamically reconfigurable FPGA partitioning. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho |
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
placement constraint, physical design, floorplanning |
| 1 | Chris C. N. Chu, Evangeline F. Y. Young |
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion Estimation with Buffer Planning in Floorplan Design. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang |
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong |
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing Seung Yuen, Fung Yu Young |
Slicing floorplan with clustering constraints. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang |
Slicing floorplans with range constraint. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong |
Floorplan area minimization using Lagrangian relaxation. |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang |
Slicing floorplans with boundary constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Fung Yu Young, Chris C. N. Chu, D. F. Wong |
Generation of Universal Series-Parallel Boolean Functions. |
J. ACM |
1999 |
DBLP DOI BibTeX RDF |
series-parallel Boolean functions, universal functions, FPGA, technology mapping |
| 1 | Fung Yu Young, D. F. Wong |
Slicing floorplans with range constraint. |
ISPD |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Fung Yu Young, D. F. Wong |
Slicing Floorplans with Boundary Constraint. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning and interconnect planning. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Fung Yu Young, D. F. Wong |
Slicing floorplans with pre-placed modules. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | F. Y. Young, D. F. Wong |
How good are slicing floorplans? |
Integration |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Fung Yu Young, D. F. Wong |
How good are slicing floorplans?. |
ISPD |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Fung Yu Young, D. F. Wong |
On the Construction of Universal Series-Parallel Functions for Logic Module Design. |
ICCD |
1997 |
DBLP BibTeX RDF |
|
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