| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton |
Combinational techniques for sequential equivalence checking.  |
FMCAD  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Massimo Roselli |
Impacting verification closure using formal analysis. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Peter Böhm |
A framework for incremental modelling and verification of on-chip protocols. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Eyad Alkassar, Ernie Cohen, Mark A. Hillebrand, Hristo Pentchev |
Modular specification and verification of interprocess communication. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Leopold Haller, Satnam Singh |
Relieving capacity limits on FPGA-based SAT-solvers. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Alexander Nadel |
Boosting minimal unsatisfiable core extraction. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Roderick Bloem, Natasha Sharygina (eds.) |
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2010, Lugano, Switzerland, October 20-23 |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Gadiel Auerbach, Fady Copty, Viresh Paruthi |
Formal verification of arbiters using property strengthening and underapproximations. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow |
Automated formal verification of processors based on architectural models. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | B. A. Krishna, Anamaya Sullerey, Alok Jain |
Formal verification of an ASIC ethernet switch block. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Michael Kuperstein, Martin T. Vechev, Eran Yahav |
Automatic inference of memory fences. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Lopamudra Sen, Amit Roy, Supriya Bhattacharjee, Bijitendra Mittra, Subir K. Roy |
DFT logic verification through property based formal methods - SOC to IP. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jun Sawada |
Automatic verification of estimate functions with polynomials of bounded functions. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Warren A. Hunt |
Verifying VIA Nano microprocessor components. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Niklas Eén, Alan Mishchenko, Nina Amla |
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Johannes Kinder, Helmut Veith |
Precise static analysis of untrusted driver binaries. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz |
Path predicate abstraction by complete interval property checking. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jason Baumgartner, Michael L. Case, Hari Mony |
Coping with Moore's Law (and more): Supporting arrays in state-of-the-art model checkers. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Nishant Sinha |
Modular bug detection with inertial refinement. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Malay K. Ganai |
Propelling SAT and SAT-based BMC using careset. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Moshe Emmer, Zurab Khasidashvili, Konstantin Korovin, Andrei Voronkov |
Encoding industrial hardware verification problems into effectively propositional logic. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Alfons Laarman, Jaco van de Pol, Michael Weber 0002 |
Boosting multi-core reachability performance with shared hash tables. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang |
Scalable and precise program analysis at NEC. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Cimatti, Andrea Micheli, Iman Narasamdya, Marco Roveri |
Verifying SystemC: A software model checking approach. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Christoph M. Wintersteiger, Youssef Hamadi, Leonardo Mendonça de Moura |
Efficiently solving quantified bit-vector formulas. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jad Hamza, Barbara Jobstmann, Viktor Kuncak |
Synthesis for regular specifications over unbounded domains. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | ShengYu Shen, Ying Qin, Jianmin Zhang, Sikun Li |
A halting algorithm to determine the existence of decoder. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Joseph Sifakis |
Embedded systems design - Scientific challenges and work directions. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sumit Gulwani |
Dimensions in program synthesis. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Anders Franzén, Alessandro Cimatti, Alexander Nadel, Roberto Sebastiani, Jonathan Shalev |
Applying SMT in symbolic execution of microcode. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Thomas Ball, Ella Bounimova, Rahul Kumar, Vladimir Levin |
SLAM2: Static driver verification with under 4% false alarms. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Eyad Alkassar, Ernie Cohen, Mark A. Hillebrand, Mikhail Kovalev, Wolfgang J. Paul |
Verifying shadow page table algorithms. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Pierluigi Nuzzo, Alberto Puggelli, Sanjit A. Seshia, Alberto L. Sangiovanni-Vincentelli |
CalCS: SMT solving for non-linear convex constraints. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Michael Siegel |
Achieving earlier verification closure using advanced formal verification. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hana Chockler |
PINCETTE - Validating changes and upgrades in networked software. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Saddek Bensalem, Marius Bozga, Axel Legay, Thanh-Hung Nguyen, Joseph Sifakis, Rongjie Yan |
Incremental component-based construction and verification using invariants. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Viresh Paruthi |
Large-scale application of formal verification: From fiction to fact. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sicun Gao, Malay K. Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund M. Clarke |
Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, Alexander Nadel |
SAT-based semiformal verification of hardware. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Dirk Beyer, M. Erkan Keremoglu, Philipp Wendler |
Predicate abstraction with adjustable-block encoding. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sagar Chaki, Arie Gurfinkel, Ofer Strichman |
Decision diagrams for linear arithmetic. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Könighofer, Georg Hofferek, Roderick Bloem |
Debugging formal specifications using simple counterstrategies. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jesse D. Bingham, John Erickson, Gaurav Singh, Flemming Andersen |
Industrial strength refinement checking. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | William Denman, Behzad Akbarpour, Sofiène Tahar, Mohamed H. Zaki, Lawrence C. Paulson |
Formal verification of analog designs using MetiTarski. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alessandro Cimatti, Jori Dubrovin, Tommi A. Junttila, Marco Roveri |
Structure-aware computation of predicate abstraction. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Saqib Sohail, Fabio Somenzi |
Safety first: A two-stage algorithm for LTL games. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Byron Cook, Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jirí Simsa, Satnam Singh, Viktor Vafeiadis |
Finding heap-bounds for hardware synthesis. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Zurab Khasidashvili, Gavriel Gavrielov, Tom Melham |
Assume-guarantee validation for STE properties within an SVA environment. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Baumgartner, Hari Mony, Michael L. Case, Jun Sawada, Karen Yorav |
Scalable conditional equivalence checking: An automated invariant-generation based approach. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Zurab Khasidashvili, Daher Kaiss, Doron Bustan |
A compositional theory for post-reboot observational equivalence checking of hardware. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | |
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA |
FMCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Malay K. Ganai, Franjo Ivancic |
Efficient decision procedure for non-linear arithmetic constraints using CORDIC. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sergey Tverdyshev |
A verified platform for a gate-level electronic control unit. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yakir Vizel, Orna Grumberg |
Interpolation-sequence based model checking. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Roderick Bloem, Karin Greimel, Thomas A. Henzinger, Barbara Jobstmann |
Synthesizing robust systems. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael L. Case, Hari Mony, Jason Baumgartner, Robert Kanzelman |
Enhanced verification by temporal decomposition. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Leonardo Mendonça de Moura, Nikolaj Bjørner |
Generalized, efficient array decision procedures. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian Keng, Andreas G. Veneris |
Scaling VLSI design debugging with interpolation. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Zhou |
Retiming and resynthesis with sweep are complete for sequential transformation. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom van den Broek, Julien Schmaltz |
Towards a formally verified network-on-chip. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Zurab Khasidashvili, Mahmoud Kinanah, Andrei Voronkov |
Verifying equivalence of memories using a first order logic theorem prover. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jyotirmoy V. Deshmukh, E. Allen Emerson |
Verification of recursive methods on tree-like data structures. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Ray, Warren A. Hunt Jr. |
Connecting pre-silicon and post-silicon verification. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | John W. O'Leary, Murali Talupur, Mark R. Tuttle |
Protocol verification using flows: An industrial experience. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Dirk Beyer, Alessandro Cimatti, Alberto Griggio, M. Erkan Keremoglu, Roberto Sebastiani |
Software model checking via large-block encoding. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | He Zhu, Fei He, William N. N. Hung, Xiaoyu Song, Ming Gu |
Data mining based decomposition for assume-guarantee reasoning. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Levent Erkök, Magnus Carlsson, Adam Wick |
Hardware/software co-verification of cryptographic algorithms using Cryptol. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnan Kailas, Viresh Paruthi, Brian Monwai |
Formal verification of correctness and performance of random priority-based arbiters. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Angelo Brillout, Daniel Kroening, Thomas Wahl |
Mixed abstractions for floating-point arithmetic. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer, Jim Holt |
MCC: A runtime verification tool for MCAPI user applications. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Pieter H. Hartel, Theo C. Ruys, Marc C. W. Geilen |
Scheduling Optimisations for SPIN to Minimise Buffer Requirements in Synchronous Data Flow. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David S. Hardin |
Invited Tutorial: Considerations in the Design and Verification of Microprocessors for Safety-Critical and Security-Critical Applications. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Roopsha Samanta, Jyotirmoy V. Deshmukh, E. Allen Emerson |
Automatic Generation of Local Repairs for Boolean Programs. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang |
BackSpace: Formal Analysis for Post-Silicon Debug. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Yan, Mark R. Greenstreet |
Verifying an Arbiter Circuit. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anna Slobodová |
Formal Verification of Hardware Support for Advanced Encryption Standard. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Federico Mari, Igor Melatti, Ivano Salvo, Enrico Tronci, Lorenzo Alvisi, Allen Clement, Harry C. Li |
Model Checking Nash Equilibria in MAD Distributed Systems. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jesse D. Bingham |
Automatic Non-Interference Lemmas for Parameterized Model Checking. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Cindy Eisner, Dana Fisman |
Augmenting a Regular Expression-Based Temporal Logic with Local Variables. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Böhm, Tom Melham |
A Refinement Approach to Design and Verification of On-Chip Communication Protocols. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alan Mishchenko, Robert K. Brayton |
Recording Synthesis History for Sequential Verification. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Arie Gurfinkel, Sagar Chaki |
Combining Predicate and Numeric Abstraction for Software Model Checking. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Per Bjesse |
Word-Level Sequential Memory Abstraction for Model Checking. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Armin Biere, Robert Brummayer |
Consistency Checking of All Different Constraints over Bit-Vectors within a SAT Solver. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Murali Talupur, Mark R. Tuttle |
Going with the Flow: Parameterized Verification Using Message Flows. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Whitman Smith, David L. Dill |
Automatic Formal Verification of Block Cipher Implementations. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Gianpiero Cabodi, Paolo Camurati, Luz Garcia, Marco Murciano, Sergio Nocco, Stefano Quer |
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alessandro Cimatti, Robert B. Jones (eds.) |
Formal Methods in Computer-Aided Design, FMCAD 2008, Portland, Oregon, USA, 17-20 November 2008 |
FMCAD |
2008 |
DBLP BibTeX RDF |
|
| 1 | Dan Goldwasser, Ofer Strichman, Shai Fine |
A Theory-Based Decision Heuristic for DPLL(T). |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Baumgartner, Hari Mony, Adnan Aziz |
Optimal Constraint-Preserving Netlist Simplification. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Warren A. Hunt Jr., Robert Bellarmine Krug, Sandip Ray, William D. Young |
Mechanized Information Flow Analysis through Inductive Assertions. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nishant Sinha |
Symbolic Program Analysis Using Term Rewriting and Generalization. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Miquel Bofill, Robert Nieuwenhuis, Albert Oliveras, Enric Rodríguez-Carbonell, Albert Rubio |
A Write-Based Solver for SAT Modulo the Theory of Arrays. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Deian Tabakov, Gila Kamhi, Moshe Y. Vardi, Eli Singerman |
A Temporal Language for SystemC. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony |
Invariant-Strengthened Elimination of Dependent State Elements. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hana Chockler, Arie Gurfinkel, Ofer Strichman |
Beyond Vacuity: Towards the Strongest Passing Formula. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | George Hagen, Cesare Tinelli |
Scaling Up the Formal Verification of Lustre Programs with SMT-Based Techniques. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Bu, You Li, Linzhang Wang, Xuandong Li |
BACH : Bounded ReAchability CHecker for Linear Hybrid Automata. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Orna Kupferman, Wenchao Li, Sanjit A. Seshia |
A Theory of Mutations with Applications to Vacuity, Coverage, and Fault Tolerance. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
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