Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Nicholas Weaver, John R. Hauser, John Wawrzynek	The SFRA: a corner-turn FPGA architecture.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
6	Sunwoo Kim, Won W. Ro	FPGA implementation of highly parallelized decoder logic for network coding (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, network coding, fpga implementation, galois field arithmetic
6	Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu	A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	loongson, multi-fpga, fpga, evaluation, verification, emulation
6	Alastair M. Smith, Steven J. E. Wilton, Joydip Das	Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.	FPGA	2009	DBLP DOI BibTeX RDF	fpga modeling, wirelength estimation, fpga, architecture design
6	Lerong Cheng, Yan Lin, Lei He	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA power model, FPGA architecture
6	Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan	CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA accelerators, c-to-gates, FPGA, high-performance computing, reconfigurable computing
6	Yan Lin, Fei Li, Lei He	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
6	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
5	Yi Shan, Bo Wang, Jing Yan, Yu Wang 0002, Ning-Yi Xu, Huazhong Yang	FPMR: MapReduce framework on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA framework, RankBoost, MapReduce
5	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
5	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
5	Donglai Dai, Aniruddha Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
5	Marcus Dutton, David C. Keezer	An architecture for graphics processing in an FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, scalability, architecture, flexibility, gpu
5	Y. Hamid, Martin Langhammer	Multiplier architectures for FPGA double precision functions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, floating point
5	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
5	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
5	Yangyang Pan, Tong Zhang	DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dram-based fpga, memory stacking, 3d integration
5	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, voter insertion, fpga, algorithm, reliability, synchronization, tmr
5	Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou	Accelerating Monte Carlo based SSTA using FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, monte carlo, SSTA
5	Peter A. Jamieson, Keneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
5	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
5	Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng	FPGA prototyping of an amba-based windows-compatible SoC.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, microsoft windows, amba, x86
5	Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.	FPGA	2010	DBLP DOI BibTeX RDF	conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
5	JIanDe Yu, JinMei Lai	A novel minloop SB design to improve FPGA routability.	FPGA	2009	DBLP DOI BibTeX RDF	minimum-loop-size maximization method, minloop switch box, routing resources design, fpga
5	Daniel L. Ly, Paul Chow	A high-performance FPGA architecture for restricted boltzmann machines.	FPGA	2009	DBLP DOI BibTeX RDF	neural network hardware, restricted boltzmann machines, scalable hardware designs, fpga, high-performance computing, complexity reduction
5	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, network on chip, multiprocessor
5	Ray Bittner	Bus mastering PCI express in an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	bus mastering, pcie, performance, fpga, design, pci express
5	Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon	FPGA implementation of real-time skin color detection with mean-based surface flattening.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, hardware design, skin detection
5	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
5	Claudio Favi, Edoardo Charbon	A 17ps time-to-digital converter implemented in 65nm FPGA technology.	FPGA	2009	DBLP DOI BibTeX RDF	65nm fpga, deep sub-nanosecond time resolution, high-speed readout, time-correlated instrumentation, time-to-digital converters, ultra-fast digital electronics, optical communications, tdc
5	Liu Ling, Neal Oliver, Chitlur Bhushan, Wang Qigang, Alvin Chen, Shen Wenbo, Yu Zhihong, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Liu Dong, Prabhat Gupta	High-performance, energy-efficient platforms using in-socket FPGA accelerators.	FPGA	2009	DBLP DOI BibTeX RDF	in-socket accelerator, fpga, agility
5	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
5	Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner	Fpga-based face detection system using Haar classifiers.	FPGA	2009	DBLP DOI BibTeX RDF	haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost
5	Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou	Implementation of a genetic algorithm on a virtex-ii pro FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	multiplier blocks, genetic algorithm, fpga, fitness functions
5	Server Kasap, Khaled Benkrid, Ying Liu	A high performance fpga-based implementation of position specific iterated blast.	FPGA	2009	DBLP DOI BibTeX RDF	psi-blast, fpga, blast, handel c
5	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, architecture, cad
5	Edward C. Lin, Rob A. Rutenbar	A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.	FPGA	2009	DBLP DOI BibTeX RDF	dsp, in silico vox, fpga, speech recognition
5	Gaurav Mittal, David Zaretsky, Prithviraj Banerjee	Streaming implementation of a sequential decompression algorithm on an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	fix., fpga, system-on-chip, binary translation, hardware-software co-design, streaming architecture
5	Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	HW/SW methodologies for synchronization in FPGA multiprocessors.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, synchronization, multiprocessors
5	Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox	FPGA technology mapping with encoded libraries andstaged priority cuts.	FPGA	2009	DBLP DOI BibTeX RDF	priority cuts, fpga, synthesis, technology mapping
5	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt	FPGA-based front-end electronics for positron emission tomography.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, localization, timing, positron emission tomography
5	Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Blliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003	Intel® atomTM processor core made FPGA-synthesizable.	FPGA	2009	DBLP DOI BibTeX RDF	intel atom, synthesizable core, fpga, emulator
5	Roto Le, Sherief Reda, R. Iris Bahar	High-performance, cost-effective heterogeneous 3D FPGA architectures.	FPGA	2009	DBLP DOI BibTeX RDF	through silicon via, fpga, heterogeneous, 3d ic, switch box
5	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
5	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
5	Keith So	Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals.	FPGA	2008	DBLP DOI BibTeX RDF	lexicographic search, negotiated congestion, timing-driven routing, FPGA
5	Mingjie Lin	The amorphous FPGA architecture.	FPGA	2008	DBLP DOI BibTeX RDF	amorphous, FPGA, architecture, performance analysis
5	Jose de Jesus Rangel-Magdaleno, René de Jesús Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez	FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors.	FPGA	2008	DBLP DOI BibTeX RDF	bar breakage, FPGA, embedded systems
5	Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong	FPGA interconnect design using logical effort.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, logical effort
5	Wei Mark Fang, Jonathan Rose	Modeling routing demand for early-stage FPGA architecture development.	FPGA	2008	DBLP DOI BibTeX RDF	model, FPGA, routing, architecture
5	Scott Sirowy, Greg Stitt, Frank Vahid	C is for circuits: capturing FPGA circuits as sequential code for portability.	FPGA	2008	DBLP DOI BibTeX RDF	sequential code, FPGA, synthesis, portability, circuit design
5	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck	Fpga-based data acquisition system for a positron emission tomography (PET) scanner.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, positron emission tomography
5	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
5	Luis Miguel Contreras-Medina, René de Jesús Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz	FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, embedded systems, vibration analysis
5	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	A novel FPGA logic block for improved arithmetic performance.	FPGA	2008	DBLP DOI BibTeX RDF	6.2 compressor, carry-chain, compressor tree, multi-operand addition, FPGA, arithmetic circuits
5	David Sheldon, Frank Vahid	A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA
5	Jason Cong, Wei Jiang	Pattern-based behavior synthesis for FPGA resource reduction.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, pattern, behavior synthesis
5	Kevin Camera, Robert W. Brodersen	An integrated debugging environment for FPGA computing platforms.	FPGA	2008	DBLP DOI BibTeX RDF	simulation, FPGA, design, verification
5	Xiaojun Wang, Miriam Leeser	Efficient FPGA implementation of qr decomposition using a systolic array architecture.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA
5	Amin Ansari, Keyvan Amiri	Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.	FPGA	2008	DBLP DOI BibTeX RDF	deinterleaver, pulse train, FPGA, parallel architecture
5	N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung	Measuring and modeling FPGA clock variability.	FPGA	2008	DBLP DOI BibTeX RDF	within-die variability, modeling, FPGA, process variation, clock skew
5	Mingjie Lin, Abbas El Gamal	A routing fabric for monolithically stacked 3D-FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis, routing architecture
5	Nicholas Weaver, Vern Paxson, José M. González	The shunt: an FPGA-based accelerator for network intrusion prevention.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, intrusion detection, hardware acceleration, NIC
5	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
5	Kevin Oo Tinmaung, David Howland, Russell Tessier	Power-aware FPGA logic synthesis using binary decision diagrams.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, binary decision diagram, dynamic power
5	Bita Gorjiara, Daniel Gajski	FPGA-friendly code compression for horizontal microcoded custom IPs.	FPGA	2007	DBLP DOI BibTeX RDF	dictionary-based compression, microcoded architectures, no-instruction-set computer, FPGA, memory optimization
5	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
5	Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun	A practical FPGA-based framework for novel CMP research.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA-based emulation, transactional memory, chip multi-processor
5	Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon	Magnetic tunnelling junction based FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	magnetic tunneling junction, FPGA, non volatility
5	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong	Performance benefits of monolithically stacked 3D-FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis
5	Norbert Pramstaller, Christian Rechberger, Vincent Rijmen	A compact FPGA implementation of the hash function whirlpool.	FPGA	2006	DBLP DOI BibTeX RDF	compact hardware implementation, FPGA, hash function, whirlpool
5	Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy	Power-aware RAM mapping for FPGA embedded memory blocks.	FPGA	2006	DBLP DOI BibTeX RDF	embedded memory block, FPGA, dynamic power
5	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Embedded floating-point units in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPU, FPGA, floating-point, FPGA architecture
5	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
5	Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev	64-bit floating-point FPGA matrix multiplication.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, matrix multiplication, floating-point
5	Ian Kuon, Aaron Egier, Jonathan Rose	Design, layout and verification of an FPGA using automated tools.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
5	Haoyu Song, John W. Lockwood	Efficient packet classification for network intrusion detection using FPGA.	FPGA	2005	DBLP DOI BibTeX RDF	BV, tree bitmap, FPGA, reconfigurable hardware, packet classification, TCAM, NIDS
5	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA redundancy, interconnect faults, fault tolerance, interconnect model, yield enhancement, yield prediction, catastrophic faults, FPGA interconnect
5	Deming Chen, Jason Cong, Fei Li, Lei He	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
5	Wang Chen, Panos Kosmas, Miriam Leeser, Carey Rappaport	An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm.	FPGA	2004	DBLP DOI BibTeX RDF	finite-difference time-domain, FPGA, hardware acceleration, hardware implementation, FDTD
5	Fei Li, Yan Lin, Lei He, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
5	Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck	Exploration of pipelined FPGA interconnect structures.	FPGA	2004	DBLP DOI BibTeX RDF	PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations
5	Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek	Post-placement C-slow retiming for the xilinx virtex FPGA.	FPGA	2003	DBLP DOI BibTeX RDF	C-slow retiming, FPGA CAD, FPGA optimization, retiming
5	Janette Frigo, Maya Gokhale, Dominique Lavenier	Evaluation of the streams-C C-to-FPGA compiler: an applications perspective.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler
5	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems. (PDF / PS)	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
4	Taiga Takata, Yusuke Matsunaga	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, technology mapping
4	Marc-Andre Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
4	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
4	Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell	A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpgas, bioinformatics, sequence alignment, data dependency analysis, smith-waterman algorithm
4	Yi-Hua E. Yang, Viktor K. Prasanna	High throughput and large capacity pipelined dynamic search tree on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	2-3 tree, in-place update, ip forwarding, pipelined tree, b-tree, dynamic update, incremental update, openflow
4	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
4	Kenneth M. Zick, John P. Hayes	On-line sensing for healthier FPGA systems.	FPGA	2010	DBLP DOI BibTeX RDF	on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management
4	Rahul Bhattachrya, Santosh Biswas, Siddhartha Mukhopadhyay	FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	ams testing, concurrent test development, behavioral modeling
4	Shepard Siegel, Mike Wirthlin	FPGA-2010 pre-conference workshop on open-source for FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, open-source
4	Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao, Russell Tessier	Scalable network virtualization using FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, virtual networks
4	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, partial reconfiguration
4	Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong	Building a faster boolean matcher using bloom filter.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, SAT, bloom filter, boolean matching, re-synthesis
4	Gregory Lucas, Chen Dong, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
4	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Energy reduction with run-time partial reconfiguration (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, energy
4	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port