Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Sudip K. Nag, Rob A. Rutenbar	Performance-driven simultaneous place and route for island-style FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout
4	Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins	Compiling and Optimizing Image Processing Algorithms for FPGAs.	CAMP	2000	DBLP DOI BibTeX RDF	SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms
3	Jason Lee, Lesley Shannon	Predicting the performance of application-specific NoCs implemented on FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability
3	Chen Huang, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
3	Crina Costea, Florent Bernard, Viktor Fischer, Robert Fouquet	Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
3	Quang Dinh, Deming Chen, Martin D. F. Wong	A routing approach to reduce glitches in low power FPGAs.	ISPD	2009	DBLP DOI BibTeX RDF	glitch reduction, path balancing, fpgas, routing, low power
3	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
3	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
3	Stephen Neuendorffer, Kees A. Vissers	Streaming Systems in FPGAs.	SAMOS	2008	DBLP DOI BibTeX RDF	digital convergence, FPGAs, dataflow
3	Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
3	Christoph Bösch, Jorge Guajardo, Ahmad-Reza Sadeghi, Jamshid Shokrollahi, Pim Tuyls	Efficient Helper Data Key Extractor on FPGAs.	CHES	2008	DBLP DOI BibTeX RDF	Intrinsic PUF, Fuzzy Extractor, Helper Data Algorithm, FPGAs, Implementation, Physical Unclonable Functions
3	Bin Zhou, David Hwang	Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	Pipeline FFTs, FPGAs
3	Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray	Reconfigurable PDA for the Visually Impaired Using FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGAs, embedded systems, Assistive technology, system on a chip
3	Xiaofang Wang, Swetha Thota	Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGAs, multiprocessor, network-on-chip
3	Steve Trimberger	Security in SRAM FPGAs.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	security, FPGAs, reverse-engineering, encryption, bitstream
3	Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan	Thermal characterization and optimization in platform FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal
3	Vishal Suthar, Shantanu Dutt	High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
3	Hasan Arslan, Shantanu Dutt	An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	bump and refit paradigm, bumping cost, hop-based routing, switchbox, FPGAs, detailed routing, MST
3	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	scheduling, optimizations, FPGAs, compilers, binary translation, chaining, hardware synthesis
3	Vinay Verma, Shantanu Dutt, Vishal Suthar	Efficient on-line testing of FPGAs with provable diagnosabilities.	DAC	2004	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
3	Yajun Ran, Malgorzata Marek-Sadowska	Crosstalk noise in FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGAs, noise, crosstalk, switch box
3	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
3	Pedro C. Diniz, Joonseok Park	Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.	FCCM	2003	DBLP DOI BibTeX RDF	Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs)
3	Chandra Mulpuri, Scott Hauck	Runtime and quality tradeoffs in FPGA placement and routing.	FPGA	2001	DBLP DOI BibTeX RDF	fast CAD for FPGAs, FPGAs, routing, computer-aided design, placement
3	Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi	Hybrid Data/Configuration Caching for Striped FPGAs.	FCCM	1999	DBLP DOI BibTeX RDF	Striped FPGAs, data caching, configuration caching
3	Juri Põldre, Kalle Tammemäe, Marek Mandre	Modular Exponent Realization on FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	Joy Shetler, Brian Hemme, Chia Yang, Christopher Hinsz	Prototyping New ILP Architectures Using FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	John M. Emmert, Akash Randhar, Dinesh Bhatia	Fast Floorplanning for FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	Reiner W. Hartenstein, Michael Herz, Frank Gilbert	Designing for Xilinx XC6200 FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo Oliveira, Konstantin Kondratjuk	Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	Robert Macketanz, Wolfgang Karl	JVX - A Rapid Prototyping System Based on Java and FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	István Vassányi	Implementing Processor Arrays on FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch	A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
3	Neil Woolfries, Patrick Lysaght, Stephen Marshall, Gordon McGregor, David Robinson	Fast Adaptive Image Processing in FPGAs Using Stack Filters.	FPL	1998	DBLP DOI BibTeX RDF
3	Elena Cerro-Prada, Philip James-Roxby	High Speed Low Level Image Processing on FPGAs Using Distributed Arithmetic.	FPL	1998	DBLP DOI BibTeX RDF
3	Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara	On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Look-up table FPGAs, universal fault diagnosis, diagnosis complexity, C-diagnosable
3	Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
3	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
3	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
3	Mahesh Mehendale, M. K. Ram Prasad	AATMA: an algorithm for technology mapping for antifuse-based FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	AATMA, antifuse-based FPGAs, logic module structure, complex functions, signature-matching based approach, mapping quality, logic module architectures, field programmable gate arrays, directed graphs, combinational circuits, logic CAD, technology mapping, execution times
3	A. Pal, R. K. Gorai, V. V. S. S. Raju	Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
3	Marco Platzner, Bernhard Rinner, Reinhold Weiss	A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs.	PDP	1995	DBLP DOI BibTeX RDF	distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation
3	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
2	Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres	A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.	FPL	2011	DBLP DOI BibTeX RDF	ElectroMagnetic Analysis (EMA), Process Characterisation, Field-Programmable Gate Arrays (FPGAs), Ring Oscillator
2	Markus Happe, Andreas Agne, Christian Plessl	Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Azadeh Nazemi, Cesar Ortega-Sanchez, Iain Murray	Digital Talking Book Player for the Visually Impaired Using FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez	Robustness Analysis of Different AES Implementations on SRAM Based FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Rizwan Ashraf, Ouns Mouri, Rami Jadaa, Ronald F. DeMara	Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Rafael A. Arce-Nazario, José R. Ortiz-Ubarri	Enumeration of Costas Arrays Using GPUs and FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada	Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Ye Lu, John V. McCanny, Sakir Sezer	The Impact of Global Routing on the Performance of NoCs in FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Imanol Martinez	Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Lu Sun, Hoang Le, Viktor K. Prasanna	Optimizing Decomposition-Based Packet Classification Implementation on FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Ameer Abdelhadi, Guy G. F. Lemieux	Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Hanaa M. Hussain, Khaled Benkrid, Ahmet T. Erdogan, Huseyin Seker	Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Jacob Couch, Peter Athanas	An Analysis of Implanted Antennas in Xilinx FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps	Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
2	Frantz Iwu	Scalable Fualt Detection for FPGAs.	HASE	2010	DBLP DOI BibTeX RDF	FPGAs, Analysis, Component-based design
2	Kaveh Elizeh, Nicola Nicolici	Embedded memory binding in FPGAs.	DAC	2010	DBLP DOI BibTeX RDF	FPGA, memory, binding
2	René Müller, Jens Teubner	FPGAs: a new point in the database design space.	EDBT	2010	DBLP DOI BibTeX RDF	FPGA, VLSI, hardware acceleration, data processing
2	Julien Lamoureux, Scott Miller, Mihai Sima	Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	shift-and-add arithmetic, fpga, cordic, coarse-grained
2	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
2	Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
2	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
2	Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu	Towards scalable placement for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, convex optimization, quadratic placement, bipartite matching
2	Kuen Hung Tsoi, Wayne Luk	Axel: a heterogeneous cluster with FPGAs and GPUs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, heterogeneous cluster
2	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
2	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
2	Mike Brugge, Mohammed A. S. Khalid	Design and evaluation of a parameterizable NoC router for FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, architecture, system-on-chip, network-on-chip, design space exploration, router
2	Gregory Lucas, Chen Dong, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
2	Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
2	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
2	Doris Chen, Deshanand Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	mtbf, fpga, metastability
2	Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh	Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Ling Liu, Oleksii Morozov	A Process-Oriented Streaming System Design Paradigm for FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Julien Francq, Céline Thuillet	Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Jochen Strunk, Johannes Hiltscher, Wolfgang Rehm, Heiko Schick	Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Janardhan Singaraju, John A. Chandy	Parallel Data Sort Using Networked FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis	Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, David Hwang	Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs.	ReConFig	2010	DBLP DOI BibTeX RDF
2	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
2	Kenneth M. Zick, John P. Hayes	On-line sensing for healthier FPGA systems.	FPGA	2010	DBLP DOI BibTeX RDF	on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management
2	Pranav Vaidya, Jaehwan John Lee, Francis Bowen, Yingzi Du, Chandima H. Nadungodage, Yuni Xia	Symbiote: a reconfigurable logic assisted data streammanagement system (RLADSMS).	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	fpgas, hardware accelerator, data stream management systems
2	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
2	Tian Song, Dongsheng Wang, Zhizhong Tang	A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	network intrusion prevention, network security, pattern matching, network intrusion detection
2	Laurent Sauvage, Sylvain Guilley, Yves Mathieu	Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.	TRETS	2009	DBLP DOI BibTeX RDF	EMA, security, FPGA, DPA, SCA, cartography
2	Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic
2	Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Self-Measurement of Combinatorial Circuit Delays in FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	FPGA, Testing, configuration, delay measurement
2	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA)
2	Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
2	Akhilesh Kumar, Mohab Anis	IR-drop management CAD techniques in FPGAs for power grid reliability.	ISQED	2009	DBLP DOI BibTeX RDF
2	Victor Dumitriu, Dennis Marcantonio, Lev Kirischian	Run-Time Component Relocation in Partially-Reconfigurable FPGAs.	CSE	2009	DBLP DOI BibTeX RDF
2	Taiga Takata, Yusuke Matsunaga	An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	FPGA, logic synthesis, technology mapping
2	Val Pevzner, Andrew A. Kennings, Andy Fox	Physical optimization for FPGAs using post-placement topology rewriting.	ISPD	2009	DBLP DOI BibTeX RDF	fpga, timing optimization, physical synthesis
2	Nikolaos Alachiotis, Euripides Sotiriades, Apostolos Dollas, Alexandros Stamatakis	Exploring FPGAs for accelerating the phylogenetic likelihood function.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Alexander Klimm, Oliver Sander, Jürgen Becker	A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Timothy R. Pearson	Real-time invariant textural object recognition with FPGAs.	EIT	2009	DBLP DOI BibTeX RDF
2	Christopher T. Johnston, Paul J. Lyons, Donald G. Bailey	User evaluation and overview of a visual language for real time image processing on FPGAs.	CHINZ	2009	DBLP DOI BibTeX RDF	FPGA, image processing, visual programming language, HDL
2	Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah	A computing origami: folding streams in FPGAs.	DAC	2009	DBLP DOI BibTeX RDF	FPGA, streaming, throughput, latency
2	Julien Lamoureux, Tony Field, Wayne Luk	Accelerating a Virtual Ecology Model with FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF