Search results for "FPL"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Daniel L. Ly, Paul Chow	A multi-FPGA architecture for stochastic Restricted Boltzmann Machines.	FPL	2009	DBLP DOI BibTeX RDF
1	Martin Danek, Jiri Kadlec, Brent E. Nelson (eds.)	19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic	FPL	2009	DBLP BibTeX RDF
1	Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMahon, Kunle Olukotun	A highly scalable Restricted Boltzmann Machine FPGA implementation.	FPL	2009	DBLP DOI BibTeX RDF
1	Jonathan Heiner, Benjamin Sellers, Michael J. Wirthlin, Jeff Kalb	FPGA partial reconfiguration via configuration scrubbing.	FPL	2009	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Qiang Wang	Improving logic density through synthesis-inspired architecture.	FPL	2009	DBLP DOI BibTeX RDF
1	Panasayya Yalla, Jens-Peter Kaps	Compact FPGA implementation of Camellia.	FPL	2009	DBLP DOI BibTeX RDF
1	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Area estimation and optimisation of FPGA routing fabrics.	FPL	2009	DBLP DOI BibTeX RDF
1	Iouliia Skliarova, Valery Sklyarov	Recursion in reconfigurable computing: A survey of implementation approaches.	FPL	2009	DBLP DOI BibTeX RDF
1	Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels	Compiler assisted runtime task scheduling on a reconfigurable computer.	FPL	2009	DBLP DOI BibTeX RDF
1	Adam Jacobs, Alan D. George, Grzegorz Cieslewski	Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space.	FPL	2009	DBLP DOI BibTeX RDF
1	Florent de Dinechin, Cristian Klein, Bogdan Pasca	Generating high-performance custom floating-point pipelines.	FPL	2009	DBLP DOI BibTeX RDF
1	Cem Savas Bassoy, Henning Manteuffel, Friedrich Mayer-Lindenberg	Sharf: An FPGA-based customizable processor architecture.	FPL	2009	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, José L. Núñez-Yáñez	Run-time resource management in fault-tolerant network on reconfigurable chips.	FPL	2009	DBLP DOI BibTeX RDF
1	Shuichi Asano, Tsutomu Maruyama, Yoshiki Yamaguchi	Performance comparison of FPGA, GPU and CPU in image processing.	FPL	2009	DBLP DOI BibTeX RDF
1	Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye	Coarse-grained dynamically reconfigurable architecture with flexible reliability.	FPL	2009	DBLP DOI BibTeX RDF
1	Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner	An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli	sFPGA2 - A scalable GALS FPGA architecture and design methodology.	FPL	2009	DBLP DOI BibTeX RDF
1	Rohit Kumar, Ann Gordon-Ross	Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs.	FPL	2009	DBLP DOI BibTeX RDF
1	Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele	Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation.	FPL	2009	DBLP DOI BibTeX RDF
1	Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano	MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.	FPL	2009	DBLP DOI BibTeX RDF
1	Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So	Operation scheduling for FPGA-based reconfigurable computers.	FPL	2009	DBLP DOI BibTeX RDF
1	Abhranil Maiti, Patrick Schaumont	Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators.	FPL	2009	DBLP DOI BibTeX RDF
1	Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi	A novel states recovery technique for the TMR softcore processor.	FPL	2009	DBLP DOI BibTeX RDF
1	Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton	Performance metrics for hybrid multi-tasking systems.	FPL	2009	DBLP DOI BibTeX RDF
1	Peter Athanas	In search of agile hardware.	FPL	2009	DBLP DOI BibTeX RDF
1	Vladimir Rozic, Ingrid Verbauwhede	Random numbers generation: Investigation of narrowtransitions suppression on FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Jiri Halak	Multigigabit network traffic processing.	FPL	2009	DBLP DOI BibTeX RDF
1	Vaughn Betz	FPGA challenges and opportunities at 40nm and beyond.	FPL	2009	DBLP DOI BibTeX RDF
1	Matt Chiu, Martin C. Herbordt	Efficient particle-pair filtering for acceleration of molecular dynamics simulation.	FPL	2009	DBLP DOI BibTeX RDF
1	Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas	A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM).	FPL	2009	DBLP DOI BibTeX RDF
1	Benjamin Sellers, Jonathan Heiner, Michael J. Wirthlin, Jeff Kalb	Bitstream compression through frame removal and partial reconfiguration.	FPL	2009	DBLP DOI BibTeX RDF
1	Jonathan Rose	The evolution of architecture exploration of programmable devices.	FPL	2009	DBLP DOI BibTeX RDF
1	Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura	Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.	FPL	2009	DBLP DOI BibTeX RDF
1	Jose Manuel Romero-Ximil, Arturo Diaz-Perez	An FPGA design for evaluating score function in protein energy calculation.	FPL	2009	DBLP DOI BibTeX RDF
1	Guillermo Botella Juan, Antonio García Ríos, Uwe H. Meyer-Baese, Manuel Rodriguez, María C. Molina, Luís Parrilla Roure	Enhanced gradient-based motion vector coprocessor.	FPL	2009	DBLP DOI BibTeX RDF
1	Bita Nezamfar, Mark Horowitz	In field, energy-performance tunable FPGA architectures.	FPL	2009	DBLP DOI BibTeX RDF
1	Qiwei Jin, David B. Thomas, Wayne Luk	Exploring reconfigurable architectures for explicit finite difference option pricing models.	FPL	2009	DBLP DOI BibTeX RDF
1	Nick Gasson, Neil C. Audsley	Synthesis of the SR programming language for complex FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly	A biophysically accurate floating point somatic neuroprocessor.	FPL	2009	DBLP DOI BibTeX RDF
1	Enno Lübbers, Marco Platzner	Cooperative multithreading in dynamically reconfigurable systems.	FPL	2009	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming.	FPL	2009	DBLP DOI BibTeX RDF
1	Heiner Giefers, Marco Platzner	Program-driven fine-grained power management for the reconfigurable mesh.	FPL	2009	DBLP DOI BibTeX RDF
1	Dong Wang, Milos D. Ercegovac, Nanning Zheng	A radix-8 complex divider for FPGA implementation.	FPL	2009	DBLP DOI BibTeX RDF
1	An Braeken, Serge Kubera, Frederik Trouillez, Abdellah Touhafi, Nele Mentens, Jo Vliegen	Secure FPGA technologies and techniques.	FPL	2009	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis, Alexandros Stamatakis, Euripides Sotiriades, Apostolos Dollas	A reconfigurable architecture for the Phylogenetic Likelihood Function.	FPL	2009	DBLP DOI BibTeX RDF
1	Roberto Gutierrez, Javier Valls, Asuncion Perez-Pascual	FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.	FPL	2009	DBLP DOI BibTeX RDF
1	Dimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos	Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths.	FPL	2009	DBLP DOI BibTeX RDF
1	Jason Agron, David L. Andrews	Building heterogeneous reconfigurable systems using threads.	FPL	2009	DBLP DOI BibTeX RDF
1	Gustavo Sutter, Jean-Pierre Deschamps	High speed fixed point dividers for FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Slavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda	A new deadlock-free fault-tolerant routing algorithm for NoC interconnections.	FPL	2009	DBLP DOI BibTeX RDF
1	Peter Alfke	Virtex-6 and Spartan-6, plus a look into the future.	FPL	2009	DBLP DOI BibTeX RDF
1	Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano	Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.	FPL	2009	DBLP DOI BibTeX RDF
1	Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker	Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.	FPL	2009	DBLP DOI BibTeX RDF
1	Joannis Sotiropoulos, Ioannis Papaefstathiou	A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems.	FPL	2009	DBLP DOI BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Data parallel FPGA workloads: Software versus hardware.	FPL	2009	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura	A virus scanning engine using a parallel finite-input memory machine and MPUs.	FPL	2009	DBLP DOI BibTeX RDF
1	Mariette Awad	FPGA supercomputing platforms: A survey.	FPL	2009	DBLP DOI BibTeX RDF
1	Enrique Cantó, Mariano Fons, Mariano López-Farcía, Rafael Ramos-Lara	Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3.	FPL	2009	DBLP DOI BibTeX RDF
1	Thomas B. Preußer, Rainer G. Spallek	Mapping basic prefix computations to fast carry-chain structures.	FPL	2009	DBLP DOI BibTeX RDF
1	Rajesh Velegalati, Jens-Peter Kaps	DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Shanyuan Gao, Andrew G. Schmidt, Ron Sass	Hardware implementation of MPI_Barrier on an FPGA cluster.	FPL	2009	DBLP DOI BibTeX RDF
1	Trevor Spiteri, George Vafiadis, Jose Luis Nunez-Yanez	A toolset for the analysis and optimization of motion estimation algorithms and processors.	FPL	2009	DBLP DOI BibTeX RDF
1	Zain-ul-Abdin	High-level programming of coarse-grained reconfigurable architectures.	FPL	2009	DBLP DOI BibTeX RDF
1	Adam Arnesen, Nathan Rollins, Michael J. Wirthlin	A multi-layered XML schema and design tool for reusing and integrating FPGA IP.	FPL	2009	DBLP DOI BibTeX RDF
1	David W. Thöni, Alfred Strey	Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm.	FPL	2009	DBLP DOI BibTeX RDF
1	Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante	Soft errors in Flash-based FPGAs: Analysis methodologies and first results.	FPL	2009	DBLP DOI BibTeX RDF
1	Ikbel Belaid, Fabrice Muller, Benjemaa Maher	Off-line placement of hardware tasks on FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera	A dynamically reconfigurable parallel pixel processing system.	FPL	2009	DBLP DOI BibTeX RDF
1	Kentaro Kokufuta, Tsutomu Maruyama	Real-time processing of local contrast enhancement on FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Caglar Kalaycioglu, Onur C. Ulusel, Ilker Hamzaoglu	Low power techniques for Motion Estimation hardware.	FPL	2009	DBLP DOI BibTeX RDF
1	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Exploiting fast carry-chains of FPGAs for designing compressor trees.	FPL	2009	DBLP DOI BibTeX RDF
1	Scott Y. L. Chin, Steven J. E. Wilton	Improving the memory footprint and runtime scalability of FPGA CAD algorithms.	FPL	2009	DBLP DOI BibTeX RDF
1	Toyokazu Takagi, Tsutomu Maruyama	Accelerating HMMER search using FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Romuald Girardey, Michael Hübner, Jürgen Becker	Dynamic reconfigurable mixed-signal architecture for safety critical applications.	FPL	2009	DBLP DOI BibTeX RDF
1	Heiner Litz, Holger Fröning, Maximilian Thürmer, Ulrich Brüning	An FPGA based verification platform for HyperTransport 3.x.	FPL	2009	DBLP DOI BibTeX RDF
1	Martin Zádník, Marco Canini, Andrew W. Moore, David J. Miller, Wei Li 0009	Tracking elephant flows in internet backbone traffic with an FPGA-based cache.	FPL	2009	DBLP DOI BibTeX RDF
1	Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch	Run-time Partial Reconfiguration speed investigation and architectural design space exploration.	FPL	2009	DBLP DOI BibTeX RDF
1	Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown	Enhancements to FPGA design methodology using streaming.	FPL	2009	DBLP DOI BibTeX RDF
1	Josef Angermeier, Abdulazim Amouri, Jürgen Teich	General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems.	FPL	2009	DBLP DOI BibTeX RDF
1	Brian H. Pratt, Michael J. Wirthlin, Michael P. Caffrey, Paul S. Graham, Keith Morgan	Noise impact of single-event upsets on an FPGA-based digital filter.	FPL	2009	DBLP DOI BibTeX RDF
1	Angel Quiros-Olozabal, Juan Manuel Barrientos-Villar, Ma de los Angeles Cifredo Chacon	Reconfiguration-based time-to-digital converter for Virtex FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis	Comparing fine-grained performance on the Ambric MPPA against an FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Maurizio Tranchero, Leonardo Maria Reyneri	Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Haile Yu, Philip H. W. Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf	Towards a unique FPGA-based identification circuit using process variations.	FPL	2009	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung	Compensating for variability in FPGAs by re-mapping and re-placement.	FPL	2009	DBLP DOI BibTeX RDF
1	J. I. Villar, J. Juan, M. J. Bellido	Efficient techniques and methodologies for embedded system design usign free hardware and open standards.	FPL	2009	DBLP DOI BibTeX RDF
1	Alejandro Nieto, Victor M. Brea, David López Vilariño	FPGA-accelerated retinal vessel-tree extraction.	FPL	2009	DBLP DOI BibTeX RDF
1	Clément Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCun	CNP: An FPGA-based processor for Convolutional Networks.	FPL	2009	DBLP DOI BibTeX RDF
1	Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire, Qingxiang Wu	Emulating Spiking Neural Networks for edge detection on FPGA hardware.	FPL	2009	DBLP DOI BibTeX RDF
1	Jason Cong	Customizable domain-specific computing.	FPL	2009	DBLP DOI BibTeX RDF
1	Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck	Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays.	FPL	2009	DBLP DOI BibTeX RDF
1	Tomasz Kryjak, Marek Gorgon	Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Florent Camarda, Jean-Christophe Prévotet, Fabienne Nouvel	Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting.	FPL	2009	DBLP DOI BibTeX RDF
1	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Using 3D integration technology to realize multi-context FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Rafael Ramos-Lara, Mariano Lopez Garcia, Enrique F. Canto Navarro, Luis Puente-Rodriguez	SVM speaker verification system based on a low-cost FPGA.	FPL	2009	DBLP DOI BibTeX RDF
1	Hironobu Morita, Minoru Watanabe	Mems optically reconfigurable gate array.	FPL	2009	DBLP DOI BibTeX RDF
1	Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala	A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.	FPL	2009	DBLP DOI BibTeX RDF
1	David Leong, Guy G. Lemieux	Replace: An incremental placement algorithm for field programmable gate arrays.	FPL	2009	DBLP DOI BibTeX RDF
1	Hans-Jörg Pfleiderer, Stefan Lachowicz	Numerically controlled oscillators using linear approximation.	FPL	2009	DBLP DOI BibTeX RDF

Publications at "FPL"( http://dblp.L3S.de/Venues/FPL )