| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Haile Yu |
FPGA interconnect sizing using extended logical effort model.   |
FPL  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenyin Fu, Katherine Compton |
Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hayden Kwok-Hay So, Robert W. Brodersen |
File system access from reconfigurable FPGA hardware processes in BORPH. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | |
FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008 |
FPL |
2008 |
DBLP BibTeX RDF |
|
| 1 | Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi |
Shared reconfigurable architectures for CMPS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong |
FPGA interconnect design using logical effort. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell |
An optimization method of DMA transfer for a general purpose reconfigurable machine. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ralf Joost, Ralf Salomon |
BOUNCE, a new approach to measure sub-nanosecond time intervals. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen McKeown, Roger Woods, John McAllister |
Power efficient DSP datapath configuration methodology for FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels |
Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomasz S. Czajkowski, Stephen Dean Brown |
Fast toggle rate computation for FPGA circuits. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Enno Lübbers, Marco Platzner |
A portable abstraction layer for hardware threads. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred Schimmler |
Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong |
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich |
No-break dynamic defragmentation of reconfigurable devices. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers |
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou |
Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle |
On the design parameters of runtime reconfigurable systems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jose Luis Nunez-Yanez, Eddie Hung, Vassilios Chouliaras |
A configurable and programmable motion estimation processor for the H.264 video codec. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivo Bolsens |
FPGA: The future platform for transforming, transporting and computing data. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich |
A comparison of embedded reconfigurable video-processing architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David B. Thomas, Wayne Luk |
Sampling from the exponential distribution using independent Bernoulli variates. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason R. Villarreal, Walid A. Najjar |
Compiled hardware acceleration of Molecular Dynamics code. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong |
Mapping and scheduling with task clustering for heterogeneous computing systems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig |
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Betul Buyukkurt, Walid A. Najjar |
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels |
Loop unrolling and shifting for reconfigurable architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Camera, Robert W. Brodersen |
An integrated debugging environment for FPGA computing platforms. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha |
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nathan A. Woods, Tom VanCourt |
FPGA acceleration of quasi-Monte Carlo in finance. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Ehliar, Per Karlström, Dake Liu |
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Danek, Jiri Kadlec, Roman Bartosinski, Lukas Kohout |
Increasing the level of abstraction in FPGA-based designs. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Christiane Beuschel, Hans-Jörg Pfleiderer |
FPGA implementation of a flexible decoder for long LDPC codes. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Schumacher, Pradip Jha |
Fast and accurate resource estimation of RTL-based designs targeting FPGAS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Pande, Joseph Zambreno |
Polymorphic wavelet architectures using reconfigurable hardware. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass |
Teaching FPGA system design via a remote laboratory facility. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya |
High-speed regular expression matching engine using multi-character NFA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa |
On-the-fly attestation of reconfigurable hardware. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch |
ATCA-based computation platform for data acquisition and triggering in particle physics experiments. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stanislaw Deniziak, Mariusz Wisniewski |
An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Koester, Wayne Luk, Geoffrey Brown |
A hardware compilation flow for instance-specific VLIW cores. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ping Chen, Andy Ye |
The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lars Bauer, Muhammad Shafique, Jörg Henkel |
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Changjian Gao, Shih-Lien Lu |
Novel FPGA based Haar classifier face detection algorithm acceleration. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi |
How fast is an FPGA in image processing? |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres |
Convergence analysis of run-time distributed optimization on adaptive systems using game theory. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
Chosen-message SPA attacks against FPGA-based RSA hardware implementations. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Kumm, M. Shahab Sanjari |
Digital hilbert transformers for FPGA-based phase-locked loops. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. Hartmann |
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki |
SAT-based resource binding for reducing critical path delays. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi |
Three-stage pipeline implementation for SHA2 using data forwarding. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki |
CVC: The C to RTL compiler for callback-based verification model. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongbing Fan, Jason Ernst, Yu-Liang Wu |
Customized Reconfigurable Interconnection Networks for multiple application SOCS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo |
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Danilin, Sergei Sawitzki, Erik Rijshouwer |
Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano |
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
Coarse-grained reconfiguration. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Theepan Moorthy, Andy Ye |
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady |
Comparing throughput and power consumption in both sequential and reconfigurable processors. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez |
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos |
A rate-based prefiltering approach to blast acceleration. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Karel Bruneel, Dirk Stroobandt |
Automatic generation of run-time parameterizable configurations. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | O. Wohlmuth |
Keynote: High performance computing based on FPGAS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Diego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-Vallvey |
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Graham Schelle, Dirk Grunwald |
Exploring FPGA network on chip implementations across various application and network loads. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Sun, Joseph Zambreno |
Mining Association Rules with systolic trees. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Langhammer |
Floating point datapath synthesis for FPGAs. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi |
A link removal methodology for Networks-on-Chip on reconfigurable systems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fujie Wong, Yajun Ha |
A low overhead fault tolerant FPGA with new connection box. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Andre Guntoro, Manfred Glesner |
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Lange, Martin Middendorf |
Hyperreconfigurable architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Kaganov, Paul Chow, Asif Lakhany |
FPGA acceleration of Monte-Carlo based credit derivative pricing. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana G. S. Santos |
NOC architecture design for multi-cluster chips. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Sghaier, Shawki Areibi, Robert Dony |
IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kimon Karras, Elias S. Manolakos |
An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Heiner Giefers |
Reconfigurable many-cores with lean interconnect. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang Le, Weirong Jiang, Viktor K. Prasanna |
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Miguel L. Silva, João Canas Ferreira |
Generation of partial FPGA configurations at run-time. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Séamas McGettrick, Dermot Geraghty, Ciarán McElroy |
An FPGA architecture for the Pagerank eigenvector problem. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun Tak Chow |
Adaptive precision technique for genetic algorithms. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede |
Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune |
A non-volatile run-time FPGA using thermally assisted switching MRAMS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst |
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David Boland, George A. Constantinides |
An FPGA-based implementation of the MINRES algorithm. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Donald G. Bailey, Christopher T. Johnston, Ni Ma |
Connected components analysis of streamed images. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto |
Operating system support for online partial dynamic reconfiguration management. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth |
An FPGA-based high-speed, low-latency trigger processor for high-energy physics. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dirk Koch, Christian Beckhoff, Jürgen Teich |
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Holger Lange, Andreas Koch |
Low-latency high-bandwidth HW/SW communication in a virtual memory environment. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng |
Direct sigma-delta modulated signal processing in FPGA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Katarina Paulsson, Michael Hübner, Jürgen Becker |
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington |
Creating unique identifiers on field programmable gate arrays using natural processing variations. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard |
Reconfigurable hardware: The holy grail of matching performance with programming productivity. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Benoît Badrignans, Reouven Elbaz, Lionel Torres |
Secure FPGA configuration architecture preventing system downgrade. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Markos Papadonikolakis, Christos-Savvas Bouganis |
Efficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shilpa Bhoj |
Thermal aware FPGA architectures and CAD. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Pongstorn Maidee, Nagib Hakim, Kia Bazargan |
FPGA family composition and effects of specialized blocks. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka |
Exploring compact design on high throughput coarse grained reconfigurable architectures. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Immacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione |
The hardware application platform of the hartes project. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")