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Publications at "FPL"( http://dblp.L3S.de/Venues/FPL )

URL (DBLP): http://dblp.uni-trier.de/db/conf/fpga

Publication years (Num. hits)
1992 (23) 1993-1994 (65) 1995 (47) 1996 (51) 1997 (52) 1998 (69) 1999 (66) 2000 (102) 2001 (75) 2002 (136) 2003 (147) 2004 (178) 2005 (149) 2006 (183) 2007 (162) 2008 (154)
Publication types (Num. hits)
inproceedings(1643) proceedings(16)
Venues (Conferences, Journals, ...)
FPL(1659)
GrowBag graphs for keyword ? (Num. hits/coverage)

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The graphs summarize 60 occurrences of 48 keywords

Results
Found 1659 publication records. Showing 1659 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Haile Yu FPGA interconnect sizing using extended logical effort model. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Wenyin Fu, Katherine Compton Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Hayden Kwok-Hay So, Robert W. Brodersen File system access from reconfigurable FPGA hardware processes in BORPH. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1 FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008 Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  BibTeX  RDF
1Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi Shared reconfigurable architectures for CMPS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong FPGA interconnect design using logical effort. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell An optimization method of DMA transfer for a general purpose reconfigurable machine. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ralf Joost, Ralf Salomon BOUNCE, a new approach to measure sub-nanosecond time intervals. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Stephen McKeown, Roger Woods, John McAllister Power efficient DSP datapath configuration methodology for FPGA. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tomasz S. Czajkowski, Stephen Dean Brown Fast toggle rate computation for FPGA circuits. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Enno Lübbers, Marco Platzner A portable abstraction layer for hardware threads. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred Schimmler Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich No-break dynamic defragmentation of reconfigurable devices. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle On the design parameters of runtime reconfigurable systems. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jose Luis Nunez-Yanez, Eddie Hung, Vassilios Chouliaras A configurable and programmable motion estimation processor for the H.264 video codec. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ivo Bolsens FPGA: The future platform for transforming, transporting and computing data. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich A comparison of embedded reconfigurable video-processing architectures. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1David B. Thomas, Wayne Luk Sampling from the exponential distribution using independent Bernoulli variates. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jason R. Villarreal, Walid A. Najjar Compiled hardware acceleration of Molecular Dynamics code. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong Mapping and scheduling with task clustering for heterogeneous computing systems. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Betul Buyukkurt, Walid A. Najjar Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels Loop unrolling and shifting for reconfigurable architectures. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Kevin Camera, Robert W. Brodersen An integrated debugging environment for FPGA computing platforms. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Nathan A. Woods, Tom VanCourt FPGA acceleration of quasi-Monte Carlo in finance. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Andreas Ehliar, Per Karlström, Dake Liu A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Martin Danek, Jiri Kadlec, Roman Bartosinski, Lukas Kohout Increasing the level of abstraction in FPGA-based designs. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Christiane Beuschel, Hans-Jörg Pfleiderer FPGA implementation of a flexible decoder for long LDPC codes. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Paul Schumacher, Pradip Jha Fast and accurate resource estimation of RTL-based designs targeting FPGAS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Amit Pande, Joseph Zambreno Polymorphic wavelet architectures using reconfigurable hardware. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass Teaching FPGA system design via a remote laboratory facility. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya High-speed regular expression matching engine using multi-character NFA. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa On-the-fly attestation of reconfigurable hardware. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch ATCA-based computation platform for data acquisition and triggering in particle physics experiments. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Stanislaw Deniziak, Mariusz Wisniewski An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Markus Koester, Wayne Luk, Geoffrey Brown A hardware compilation flow for instance-specific VLIW cores. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ping Chen, Andy Ye The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Lars Bauer, Muhammad Shafique, Jörg Henkel A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Changjian Gao, Shih-Lien Lu Novel FPGA based Haar classifier face detection algorithm acceleration. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi How fast is an FPGA in image processing? Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres Convergence analysis of run-time distributed optimization on adaptive systems using game theory. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh Chosen-message SPA attacks against FPGA-based RSA hardware implementations. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Martin Kumm, M. Shahab Sanjari Digital hilbert transformers for FPGA-based phase-locked loops. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. Hartmann Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki SAT-based resource binding for reducing critical path delays. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi Three-stage pipeline implementation for SHA2 using data forwarding. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki CVC: The C to RTL compiler for callback-based verification model. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Hongbing Fan, Jason Ernst, Yu-Liang Wu Customized Reconfigurable Interconnection Networks for multiple application SOCS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Alexander Danilin, Sergei Sawitzki, Erik Rijshouwer Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner Coarse-grained reconfiguration. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Theepan Moorthy, Andy Ye A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady Comparing throughput and power consumption in both sequential and reconfigurable processors. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos A rate-based prefiltering approach to blast acceleration. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Karel Bruneel, Dirk Stroobandt Automatic generation of run-time parameterizable configurations. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1O. Wohlmuth Keynote: High performance computing based on FPGAS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Diego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-Vallvey Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Graham Schelle, Dirk Grunwald Exploring FPGA network on chip implementations across various application and network loads. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Song Sun, Joseph Zambreno Mining Association Rules with systolic trees. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Martin Langhammer Floating point datapath synthesis for FPGAs. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi A link removal methodology for Networks-on-Chip on reconfigurable systems. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Fujie Wong, Yajun Ha A low overhead fault tolerant FPGA with new connection box. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Andre Guntoro, Manfred Glesner A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Sebastian Lange, Martin Middendorf Hyperreconfigurable architectures. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Alexander Kaganov, Paul Chow, Asif Lakhany FPGA acceleration of Monte-Carlo based credit derivative pricing. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana G. S. Santos NOC architecture design for multi-cluster chips. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ahmad Sghaier, Shawki Areibi, Robert Dony IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Kimon Karras, Elias S. Manolakos An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Heiner Giefers Reconfigurable many-cores with lean interconnect. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Hoang Le, Weirong Jiang, Viktor K. Prasanna Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Miguel L. Silva, João Canas Ferreira Generation of partial FPGA configurations at run-time. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Séamas McGettrick, Dermot Geraghty, Ciarán McElroy An FPGA architecture for the Pagerank eigenvector problem. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Chun Tak Chow Adaptive precision technique for genetic algorithms. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune A non-volatile run-time FPGA using thermally assisted switching MRAMS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1David Boland, George A. Constantinides An FPGA-based implementation of the MINRES algorithm. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Donald G. Bailey, Christopher T. Johnston, Ni Ma Connected components analysis of streamed images. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto Operating system support for online partial dynamic reconfiguration management. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth An FPGA-based high-speed, low-latency trigger processor for high-energy physics. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Dirk Koch, Christian Beckhoff, Jürgen Teich ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Holger Lange, Andreas Koch Low-latency high-bandwidth HW/SW communication in a virtual memory environment. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng Direct sigma-delta modulated signal processing in FPGA. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Katarina Paulsson, Michael Hübner, Jürgen Becker Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington Creating unique identifiers on field programmable gate arrays using natural processing variations. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard Reconfigurable hardware: The holy grail of matching performance with programming productivity. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Benoît Badrignans, Reouven Elbaz, Lionel Torres Secure FPGA configuration architecture preventing system downgrade. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Markos Papadonikolakis, Christos-Savvas Bouganis Efficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Shilpa Bhoj Thermal aware FPGA architectures and CAD. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Pongstorn Maidee, Nagib Hakim, Kia Bazargan FPGA family composition and effects of specialized blocks. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka Exploring compact design on high throughput coarse grained reconfigurable architectures. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Immacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione The hardware application platform of the hartes project. Search with DBLP WebCrawler Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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