| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Stefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild, Andreas Herkersdorf |
A framework for Open Tiled Manycore System-On-Chip.  |
FPL  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dirk Koch, Satnam Singh, Jim Tørresen (eds.) |
22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012 |
FPL |
2012 |
DBLP BibTeX RDF |
|
| 1 | Marcel Gort, Jason Helge Anderson |
Analytical placement for heterogeneous FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf |
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Abid Rafique, Nachiket Kapre, George A. Constantinides |
Enhancing performance of Tall-Skinny QR factorization using FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Robin Panda, Carl Ebeling, Scott Hauck |
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gordon Inggs, David Thomas, Simon Winberg |
Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoni Roca, José Flich, Giorgos Dimitrakopoulos |
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhongduo Lin, Charles Lo, Paul Chow |
K-means implementation on FPGA for high-dimensional data using triangle inequality. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bahram N. Uchevler, Kjetil Svarstad |
Modeling of dynamic reconfigurable systems with Haskell. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Carl Ingemarsson, Petter Kallstrom, Oscar Gustafsson |
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chung Chen, Wenhua Wang, Hai Li, Wei Zhang |
Non-volatile 3D stacking RRAM-based FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Aaron Wood, Adam Knight, Benjamin Ylvisaker, Scott Hauck |
Multi-kernel floorplanning for enhanced CGRAS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh |
From opencl to high-performance hardware on FPGAS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shadi Traboulsi, Wenlong Zhang, David Szczesny, Anas Showk, Attila Bilgic |
An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Petr Pfeifer, Zdenek Plíva |
On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas |
Optimising explicit finite difference option pricing for dynamic constant reconfiguration. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew Somerville, Kenneth B. Kent |
Improving memory support in the VTR flow. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Junfeng Chu, Mohammed Benaissa |
Low area memory-free FPGA implementation of the AES algorithm. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhenyu Guan, Justin S. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Flynn, Oliver Pell, Oskar Mencer |
Dataflow supercomputing. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Policarpo Duarte, Christos-Savvas Bouganis |
High-level linear projection circuit design optimization framework for FPGAs under over-clocking. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ghaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev |
Intra-chip physical parameter sensor for FPGAS using flip-flop metastability. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | George Eichinger, Kaushik Chowdhury, Miriam Leeser |
CRUSH: Cognitive Radio Universal Software Hardware. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Niyati Shah, Jonathan Rose |
On the difficulty of pin-to-wire routing in FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | François Philipp, Manfred Glesner |
(GECO)2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
Fault detection and avoidance of FPGA in various granularities. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano |
Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mateusz Komorkiewicz, Maciej Kluczewski, Marek Gorgon |
Floating point HOG implementation for real-time multiple object detection. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Kumm, Katharina Liebisch, Peter Zipf |
Reduced complexity single and multiple constant multiplication in floating point precision. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Alok Prakash, Christopher T. Clarke, Thambipillai Srikanthan |
Custom instructions with local memory elements without expensive DMA transfers. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Kastelan, Vladimir Marinkovic, Radomir Dzakula, Nikola Vranic, Vukota Pekovic |
Stimulation board for automated verification of touchscreen-based devices. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruben Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina |
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Hochberger, Changgong Li, Michael Raitza, Markus Vogt |
Influence of operating conditions on ring oscillator-based entropy sources in FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Daichi Kobori, Tsutomu Maruyama |
An acceleration of a graph cut segmentation with FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Haruhisa Tsuyama, Tsutomu Maruyama |
An FPGA acceleration of a level set segmentation method. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Suvarna Mane, Mostafa M. I. Taha, Patrick Schaumont |
Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri |
Deep-pipelined FPGA implementation of ellipse estimation for eye tracking. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thusitha N. Chandrapala, Amila P. Cabral, Sapumal Ahangama, Thilina S. Ambagahawaththa, Jayathu G. Samarawickrama |
Hardware implementation of motion blur removal. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Raul Torrego, Inaki Val, Eñaut Muxika, Xabier Iturbe, Khaled Benkrid |
Data coding functions for Software Defined Radios implemented on R3TOS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Minxi Jin, Tsutomu Maruyama |
A fast and high quality stereo matching algorithm on FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungwook Choi, Rob A. Rutenbar |
Hardware implementation of MRF map inference on an FPGA platform. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy Abramson, Pedro C. Diniz |
A resiliency-aware scheduling approach for FPGA configuration: Preliminary results. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Ramírez, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg |
NoC-AXI interface for FPGA-based MPSoC platforms. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc-André Daigneault, Jean-Pierre David |
Raising the abstraction level of HDL for control-dominant applications. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Amila Akagic, Hideharu Amano |
Performance analysis of fully-adaptable CRC accelerators on an FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mário P. Véstias, Horácio C. Neto, Helena Sarmento |
Sliding block Viterbi decoders in FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Adam Jacobs, Grzegorz Cieslewski, Alan D. George |
Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Henrey, Sean Edmond, Lesley Shannon, Carlo Menon |
Bio-inspired walking: A FPGA multicore system for a legged robot. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell |
Exploiting run-time reconfiguration in stencil computation. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye |
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Björn Meyer, Jörn Schumacher, Christian Plessl, Jens Forstner |
Convey vector personalities - FPGA acceleration with an openmp-like programming effort? |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto |
Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Paulo Da Cunha Possa, Sidi Ahmed Mahmoudi, Naim Harb, Carlos Valderrama |
A new self-adapting architecture for feature detection. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner |
Implementation and outcomes of FPGA-based system design in Mongolian education. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Takashi Yoza, Minoru Watanabe |
A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Oberg, Ken Eguro, Ray Bittner, Alessandro Forin |
Random decision tree body part recognition using FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Anja Niedermeier, Jan Kuper, Gerard J. M. Smit |
High level structural description of streaming applications. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Pascal Cotret, Guy Gogniat, Jean-Philippe Diguet, Jérémie Crenne |
Lightweight reconfiguration security services for AXI-based MPSoCs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoph Ruething, Andreas Agne, Markus Happe, Christian Plessl |
Exploration of ring oscillator design space for temperature measurements on FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | George Lentaris, Dionysios Diamantopoulos, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez |
Hardware implementation of stereo correspondence algorithm for the ExoMars mission. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Junichi Sawada, Hiroaki Nishi |
Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Eddie Hung, Steven J. E. Wilton |
Limitations of incremental signal-tracing for FPGA debug. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki Murakami |
Thermal-aware partitioning for 3D FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido |
Dual MicroBlaze rekeying processor for group key management. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Köllner, Nico Adler, Klaus D. Müller-Glaser |
System#: High-level synthesis of physical simulations for FPGA-based real-time execution. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk |
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanav Khurana, Pooja Gupta, Rajesh Chandrasekhara Panicker, Akash Kumar |
Development of an FPGA-based real-time P300 speller. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas P. Perry, Richard L. Walke, Rob Payne, Stefan Petko, Khaled Benkrid |
IP-XACT extensions for IP interoperability guarantees and software model generation. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bajaj Ronak, Suhaib A. Fahmy |
Evaluating the efficiency of DSP Block synthesis inference from flow graphs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gerald Hempel, Christian Hochberger, Michael Raitza |
Towards GCC-based automatic soft-core customization. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Travis Manderson, Laurence Turner |
Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rodrigo Bernardo, Luis R. Monte, Eduardo Mobilon, Valentino Corso, Arley H. Salvador, Carolina G. Neves, Cleber A. Nakandakare, Daniele R. da Silva, Luis P. F. de Barros, Ronaldo F. da Silva |
Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systems. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Masamichi Takagi, Takashi Takenaka, Hiroaki Inoue |
Dynamic query switching for complex event processing on FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria Kalenderi, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Charalampos Manifavas |
Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hanaa M. Hussain, Khaled Benkrid, Chuan Hong, Huseyin Seker |
An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfiguration. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fatma Abouelella, Karel Bruneel, Dirk Stroobandt |
Automatically exploiting regularity in applications to reduce reconfiguration memory requirements. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano |
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Atabak Mahram, Martin C. Herbordt |
CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filters. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Wang, Xi Li, Junneng Zhang, Peng Chen 0004, Xuehai Zhou |
CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | David Sheffield, Michael J. Anderson, Kurt Keutzer |
Automatic generation of application-specific accelerators for FPGAs from python loop nests. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Karel Heyse, Karel Bruneel, Dirk Stroobandt |
Mapping logic to reconfigurable FPGA routing. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bogdan Pasca |
Correctly rounded floating-point division for DSP-enabled FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Hong, Khaled Benkrid, Xabier Iturbe, Ali Ebrahim |
Design and implementation of fault-tolerant soft processors on FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rinse Wester, Christiaan Baaij, Jan Kuper |
A two step hardware design method using CλaSH. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenjuan Deng, Yiqun Zhu, Hao Feng, Zhiguo Jiang |
An efficient hardware architecture of the optimised SIFT descriptor generation. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunmeng Bi, Tsutomu Maruyama |
Real-time corner and polygon detection system on FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings |
EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, Mikel Garay, Javier Del Ser |
Fast and accurate Single Bit Error injection into SRAM Based FPGAs. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Dang Ba Khac Trieu, Tsutomu Maruyama |
A region merging approach for image segmentation on FPGA. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski |
Adaptive Sequential Monte Carlo approach for real-time applications. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ercan Kalali, Yusuf Adibelli, Ilker Hamzaoglu |
A high performance and low energy intra prediction hardware for High Efficiency Video Coding. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt |
Maximizing the reuse of routing resources in a reconfiguration-aware connection router. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zoltán Nagy, Csaba Nemes, Antal Hiba, András Kiss, Árpád Csík, Péter Szolgay |
FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Di Wang, Christopher T. Clarke, A. N. Evans |
Examination of the concept of a row-column separated median filter. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Doris Chen, Deshanand P. Singh |
Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Xin Zheng, Ethan Chen, Miodrag Potkonjak |
A Benign Hardware Trojan on FPGA-based embedded systems. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Izaan Allugundu, Pranay Puranik, Yat Piu Lo, Akash Kumar |
Acceleration of distance-to-default with hardware-software co-design. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Matthews, Lesley Shannon, Alexandra Fedorova |
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support. |
FPL |
2012 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")