Search results for "Fadi J. Kurdahi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Kiarash Amiri, Shih-Hsien Yang, Fadi J. Kurdahi, Magda El Zarki, Aditi Majumder	Collaborative video playback on a federation of tiled mobile projectors enabled by visual feedback.	MMSys	2012	DBLP DOI BibTeX RDF
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	A Multi-Granularity Power Modeling Methodology for Embedded Processors.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Amr M. A. Hussien, Muhammed S. Khairy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	A Class of Low Power Error Compensation Iterative Decoders.	GLOBECOM	2011	DBLP DOI BibTeX RDF
1	Amir Hossein Gholamipour, Ali Gorcin, Hasari Celebi, B. Ugur Töreyin, Mazen A. R. Saghir, Fadi J. Kurdahi, Ahmed M. Eltawil	Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanley Cheng, Amin Khajeh Djahromi	Low-Power Multimedia System Design by Aggressive Voltage Scaling.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Jarmo Takala (eds.)	Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece, July 19-22, 2010	ICSAMOS	2010	DBLP BibTeX RDF
1	Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.	ISQED	2010	DBLP DOI BibTeX RDF
1	Amir Hossein Gholamipour, Fadi J. Kurdahi, Ahmed M. Eltawil, Mazen A. R. Saghir	Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters.	FPL	2010	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi	Designing working systems with imperfect chips.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi	E < MC2: less energy through multi-copy cache.	CASES	2010	DBLP DOI BibTeX RDF
1	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
1	Amin Khajeh, Kiarash Amiri, Muhammed S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi	A Unified Hardware and Channel Noise Model for Communication Systems.	GLOBECOM	2010	DBLP DOI BibTeX RDF
1	Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Effect of body biasing on embedded SRAM failure.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Kiarash Amiri, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Process variation aware transcoding for low power H.264 decoding.	ESTImedia	2010	DBLP DOI BibTeX RDF
1	Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt	RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi	System-level PVT variation-aware power exploration of on-chip communication architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems
1	Mohammad A. Makhzan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
1	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Amir Hossein Gholamipour, Hamid Eslami, Ahmed M. Eltawil, Fadi J. Kurdahi	Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems.	FCCM	2009	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.	DATE	2009	DBLP BibTeX RDF
1	Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir	TRAM: A tool for Temperature and Reliability Aware Memory Design.	DATE	2009	DBLP BibTeX RDF
1	Mohammad A. Makhzan, Ahmed M. Eltawil, Fadi J. Kurdahi	Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices.	ICSAMOS	2008	DBLP DOI BibTeX RDF
1	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.	ISQED	2008	DBLP DOI BibTeX RDF	reliability, global routing, thermal
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt	Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi	PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif	Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Amin Khajeh Djahromi, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi	Cross-layer co-exploration of exploiting error resilience for video over wireless applications.	ESTImedia	2008	DBLP DOI BibTeX RDF
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	Methodology for multi-granularity embedded processor power model generation for an ESL design flow.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system-on-chip, embedded processor, power modeling, esl
1	Chunhui Zhang, Fadi J. Kurdahi	Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	low power, DSP, memory hierarchy, tiling, data locality, iteration space
1	Chunhui Zhang, Yun Long, Fadi J. Kurdahi	A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT.	J. Real-Time Image Processing	2007	DBLP DOI BibTeX RDF
1	Chunhui Zhang, Yun Long, Fadi J. Kurdahi	A scalable embedded JPEG 2000 architecture.	Journal of Systems Architecture	2007	DBLP DOI BibTeX RDF
1	Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj	Cross Layer Error Exploitation for Aggressive Voltage Scaling.	ISQED	2007	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Mohammad A. Makhzan, Stanley Cheng	Error-Aware Design.	DSD	2007	DBLP DOI BibTeX RDF
1	Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil	An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Embedded memory Yield, Defect Map, Memory Error Resilient Design, Video error concealment
1	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
1	Amin Khajeh, Shih-Yang Cheng, Ahmed M. Eltawil, Fadi J. Kurdahi	Power Management for Cognitive Radio Platforms.	GLOBECOM	2007	DBLP DOI BibTeX RDF
1	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	System level power estimation methodology with H.264 decoder prediction IP case study.	ICCD	2007	DBLP DOI BibTeX RDF
1	Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi	Limits on voltage scaling for caches utilizing fault tolerant techniques.	ICCD	2007	DBLP DOI BibTeX RDF
1	Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi	Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design.	VTC Spring	2007	DBLP DOI BibTeX RDF
1	Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi	Compile-time area estimation for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Reconfigurable computing, compiler optimization, resource estimation
1	Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif	System-Level SRAM Yield Enhancement.	ISQED	2006	DBLP DOI BibTeX RDF
1	Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil	Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low power image filter design, Memory yield enhancement, Memory-error resilient design, H.264 codec, BIST, Embedded memory, BISR
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
1	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Floorplan driven leakage power aware IP-based SoC design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	floorplan, leakage power, temperature
1	Chunhui Zhang, Yun Long, Fadi J. Kurdahi	A Scalable Embedded JPEG2000 Architecture.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Chunhui Zhang, Fadi J. Kurdahi	On combining iteration space tiling with data space tiling for scratch-pad memory systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes	Automatic compilation to a coarse-grained reconfigurable system-opn-chip.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	compilers, Reconfigurable computing, SIMD
1	Behzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi	A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	reconfigurable computing, software-defined radio
1	Fadi J. Kurdahi	Guest editorial special issue on system synthesis.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi	MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
1	Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi	Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems.	FCCM	2002	DBLP DOI BibTeX RDF
1	Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi	A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.	DATE	2002	DBLP DOI BibTeX RDF
1	Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh	Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing.	Journal of Systems Architecture	2001	DBLP DOI BibTeX RDF
1	Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh	A framework for reconfigurable computing: task scheduling and context management.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi	Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems.	DAC	2001	DBLP DOI BibTeX RDF
1	Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm	A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.	CASES	2001	DBLP DOI BibTeX RDF
1	Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh	A data scheduler for multi-context reconfigurable architectures.	ISSS	2001	DBLP BibTeX RDF
1	Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi	A constraint-based application model and scheduling techniques for power-aware systems.	CODES	2001	DBLP DOI BibTeX RDF	embedded systems software, power-aware real-time scheduling, system-level design, constraint modeling
1	Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho	MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	reconfigurable cell array, bit-correlation, dynamic reconfiguration, Single Instruction Multiple Data, multimedia applications, video compression, MPEG-2, Reconfigurable systems, data encryption, target recognition
1	Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves	Design and Implementation of the MorphoSys Reconfigurable Computing Processor.	VLSI Signal Processing	2000	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz	Guest Editors' Introduction: Configurable Computing.	IEEE Design & Test of Computers	2000	DBLP BibTeX RDF
1	Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh	MorphoSys: case study of a reconfigurable computing system targeting multimedia applications.	DAC	2000	DBLP DOI BibTeX RDF	scheduling, SIMD, MPEG-2, automatic target recognition, dynamic configuration, reconfigurable processors
1	Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh	Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.	FCCM	2000	DBLP DOI BibTeX RDF
1	Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh	Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization.	ISSS	2000	DBLP DOI BibTeX RDF
1	Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh	Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm	High-level synthesis of recoverable VLSI microarchitectures.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Min Xu, Fadi J. Kurdahi	Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho	The MorphoSys Parallel Reconfigurable System.	Euro-Par	1999	DBLP DOI BibTeX RDF
1	Guangming Lu, Ming-Hau Lee, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho	MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application.	IPPS/SPDP Workshops	1999	DBLP DOI BibTeX RDF
1	Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández	Kernel Scheduling in Reconfigurable Computing.	DATE	1999	DBLP DOI BibTeX RDF
1	Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves	The MorphoSys Dynamically Reconfigurable System-on-Chip.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
1	Dirk Stroobandt, Fadi J. Kurdahi	On the Characterization of Multi-Point Nets in Electronic Designs.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Multi-point nets, Net degree distribution, Interconnection complexity, Rent's rule
1	Min Xu, Fadi J. Kurdahi	Layout-Driven High Level Synthesis for FPGA Based Architectures.	DATE	1998	DBLP DOI BibTeX RDF
1	Min Xu, Fadi J. Kurdahi	Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	FPGAs, high-level synthesis, floorplan, binding
1	Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm	Optimal algorithms for recovery point insertion in recoverable microarchitectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt	A unified lower bound estimation technique for high-level synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Min Xu, Fadi J. Kurdahi	RTL synthesis with physical and controller information.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Min Xu, Fadi J. Kurdahi	Layout-Driven RTL Binding Techniques for High-Level Synthesis. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process
1	A. Sriram, Fadi J. Kurdahi	Behavioral Modeling of an ATM Switch using SpecCharts.	VLSI Design	1996	DBLP DOI BibTeX RDF
1	Seong Yong Ohm, Fadi J. Kurdahi, Chu Shik Jhon	An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
1	Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm	Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures.	FTCS	1995	DBLP DOI BibTeX RDF
1	Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran	On the intrinsic Rent parameter and spectra-based partitioning methodologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Champaka Ramachandran, Fadi J. Kurdahi	Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Champaka Ramachandran, Fadi J. Kurdahi	Incorporating the Controller Effects During Register Transfer Level Synthesis.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi	An Empirical Study on the Effects of Physical Design in High-Level Synthesis.	VLSI Design	1994	DBLP BibTeX RDF
1	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt	Comprehensive lower bound estimation from behavioral descriptions.	ICCAD	1994	DBLP DOI BibTeX RDF
1	D. Sreenivasa Rao, Fadi J. Kurdahi	On clustering for maximal regularity extraction.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	D. Sreenivasa Rao, Fadi J. Kurdahi	Hierarchical design space exploration for a class of digital systems.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Champaka Ramachandran	Evaluating layout area tradeoffs for high level applications.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF
1	D. Sreenivasa Rao, Fadi J. Kurdahi	Partitioning by Regularity Extraction.	DAC	1992	DBLP BibTeX RDF

Publications of "Fadi J. Kurdahi" ( http://dblp.L3S.de/Authors/Fadi_J._Kurdahi )