Search results for "Farzan Fallah"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Arash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner	Xquasher: a tool for efficient computation of multiple linear expressions.	DAC	2009	DBLP DOI BibTeX RDF	DSP transforms, common sub-expression elimination, linear expression, multiple constant multiplications, area optimization
1	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge Recycling in Power-Gated CMOS Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Farzan Fallah	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors	CoRR	2007	DBLP BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Algebraic Methods for Optimizing Constant Multiplications in Linear Systems.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	constant multiplications, DSP synthesis, high level synthesis, linear systems, common subexpression elimination, algebraic methods
1	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Massoud Pedram, Farzan Fallah	Low-leakage SRAM Design with Dual V_t Transistors.	ISQED	2006	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using MTCMOS and multi-Vt techniques.	ISLPED	2006	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
1	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge recycling in MTCMOS circuits: concept and analysis.	DAC	2006	DBLP DOI BibTeX RDF	low power design, MTCMOS, charge recycling
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Optimizing high speed arithmetic circuits using three-term extraction.	DATE	2006	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
1	Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah	An Energy Characterization Framework for Software-Based Embedded Systems.	ESTImedia	2006	DBLP DOI BibTeX RDF
1	Farzan Fallah, Massoud Pedram	Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.	ISQED	2005	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using multiple threshold voltage inverters.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
1	Tohru Ishihara, Farzan Fallah	A non-uniform cache architecture for low power system design.	ISLPED	2005	DBLP DOI BibTeX RDF	embedded systems, compiler, microprocessor, cache memory
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	An effective power mode transition technique in MTCMOS circuits.	DAC	2005	DBLP DOI BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Energy Efficient Hardware Synthesis of Polynomial Expressions.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Farzan Fallah	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.	DATE	2005	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Farzan Fallah	A cache-defect-aware code placement algorithm for improving the performance of processors.	ICCAD	2005	DBLP BibTeX RDF
1	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	Transition reduction in memory buses using sector-based encoding techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Leakage current reduction in CMOS VLSI circuits by input vector control.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis.	ASAP	2004	DBLP DOI BibTeX RDF
1	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Factoring and eliminating common subexpressions in polynomial expressions.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains.	ISQED	2003	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh	Precomputation-based Guarding for Dynamic and Leakage Power Reduction.	ICCD	2003	DBLP DOI BibTeX RDF
1	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	A Class of Irredundant Encoding Techniques for Reducing Bus Power.	Journal of Circuits, Systems, and Computers	2002	DBLP DOI BibTeX RDF
1	Farzan Fallah, Pranav Ashar, Srinivas Devadas	Functional vector generation for sequential HDL models under an observability-based code coverage metric.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	ALBORZ: Address Level Bus Power Optimization. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	Low power bus encoding, limited-weight codes, codebook-based codes
1	Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah	Reducing transitions on memory buses using sector-based encoding technique.	ISLPED	2002	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Massoud Pedram, Farzan Fallah	Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2.	ISLPED	2002	DBLP DOI BibTeX RDF
1	Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah	EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses.	DATE	2002	DBLP DOI BibTeX RDF
1	Farzan Fallah	Binary Time Frame Expansion.	IWLS	2002	DBLP BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah	Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits.	IWLS	2002	DBLP BibTeX RDF
1	Farzan Fallah	Binary time-frame expansion.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Seda Ogrenci Memik, Farzan Fallah	Accelerated SAT-based Scheduling of Control/Data Flow Graphs.	ICCD	2002	DBLP DOI BibTeX RDF
1	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	Irredundant address bus encoding for low power.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Farzan Fallah, Koichiro Takayama	A New Functional Test Program Generation Methodology.	ICCD	2001	DBLP BibTeX RDF
1	Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer	A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage.	ICCD	2001	DBLP BibTeX RDF
1	Farzan Fallah, Stan Y. Liao, Srinivas Devadas	Solving covering problems using LPR-based lower bounds.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Farzan Fallah, Pranav Ashar, Srinivas Devadas	Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.	DAC	1999	DBLP DOI BibTeX RDF
1	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
1	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian

Publications of "Farzan Fallah" ( http://dblp.L3S.de/Authors/Farzan_Fallah )