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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chao-Hung Chen, Hsien-Chin Chiu, Chih-Wei Yang, Jeffrey S. Fu, Feng-Tso Chien |
Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer.  |
Microelectronics Reliability  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
Dynamic voltage domain assignment technique for low power performance manageable cell based design. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng |
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Chien-Nan Liao, Feng-Tso Chien, Chi-Ling Wang, Hsien-Chin Chiu, Yi-Jen Chan |
A Novel Power MOSFET Structure with Shallow Junction Dual Well Design. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Feng-Tso Chien, Chien-Nan Liao, Chi-Ling Wang, Hsien-Chin Chiu |
High Performance Power MOSFETs by Wing-Cell Structure Design. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Feng-Tso Chien, Ming-Hung Lai, Shih-Tzung Su, Kou-Way Tu, Ching-Ling Cheng |
High Ruggedness Power MOSFET Design by a Self-Align p+ Process. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #6 of 6 (100 per page; Change: )
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