Search results for "Fernando Moraes"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans	Impact of C-elements in asynchronous circuits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Cristiano Lazzari, Marcelo Lubaszewski, Fernando Gehm Moraes	A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres	A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	cryptography attacks, DPA, asynchronous, SCA, GALS, design and test, DEMA
1	Luciano Ost, Guilherme Guindani, Fernando Gehm Moraes, Leandro Soares Indrusiak, Sanna Määttä	Exploring NoC-Based MPSoC Design Space with Power Estimation Models.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Arbitration and routing impact on NoC design.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski	Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Everton Carara, Gabriel Marchesan Almeida, Gilles Sassatelli, Fernando Gehm Moraes	Achieving composability in NoC-based MPSoCs through QoS management at software level.	DATE	2011	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Luciano Ost, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski	Evaluating energy consumption of homogeneous MPSoCs using spare tiles.	DATE	2011	DBLP BibTeX RDF
1	Marcelo Mandelli, Luciano Ost, Everton Carara, Guilherme Guindani, Thiago Gouvea, Guilherme Medeiros, Fernando Gehm Moraes	Energy-aware dynamic task mapping for NoC-based MPSoCs.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Gabriel Marchesan Almeida, Rémi Busseuil, Everton Alceu Carara, Nicolas Hebert, Sameer Varyani, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Fernando Gehm Moraes	Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Tales Marchesan Chaves, Everton Alceu Carara, Fernando Gehm Moraes	Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Eduardo Wächter, Adelcio Biazi, Fernando Gehm Moraes	HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin	CAFES: A framework for intrachip application modeling and communication architecture design.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Romain Prolonge, Fabien Clermidy, Leonel Tedesco, Fernando Moraes	Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots.	DSD	2011	DBLP DOI BibTeX RDF
1	Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans	Adapting a C-element design flow for low power.	ICECS	2011	DBLP DOI BibTeX RDF
1	Luciano Ost, Gabriel Marchesan Almeida, Marcelo Mandelli, Eduardo Wächter, Sameer Varyani, Gilles Sassatelli, Leandro Soares Indrusiak, Michel Robert, Fernando Moraes	Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Dynamic Task Mapping for MPSoCs.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes	Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Everton Carara, Fernando Gehm Moraes	Evaluating the impact of task migration in multi-processor systems-on-chip.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes	Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner	Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.	FPL	2010	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans	Hermes-A - An Asynchronous NoC Router with Distributed Routing.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Luciano Ost, Leandro Soares Indrusiak, Sanna Määttä, Marcelo Mandelli, Jari Nurmi, Fernando Moraes	Model-based design flow for NoC-based MPSoCs.	ICECS	2010	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans	Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.	SoCC	2010	DBLP DOI BibTeX RDF
1	Everton Carara, Fernando Moraes	Flow oriented routing for NOCS.	SoCC	2010	DBLP DOI BibTeX RDF
1	Alzemiro H. Lucas, Alexandre M. Amory, Fernando Gehm Moraes	Crosstalk Fault Tolerant NoC: Design and Evaluation.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes	HeMPS - a Framework for NoC-based MPSoC Generation.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area.	ReConFig	2009	DBLP DOI BibTeX RDF	floating point hardware, GALS design, FPGA, prototyping, embedded processor
1	Guilherme Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes	A 10 Gbps OTN Framer Implementation Targeting FPGA Devices.	ReConFig	2009	DBLP DOI BibTeX RDF	OTN, Optical Transport Network, Telecommunication Circuits, Framer, FPGA
1	Luciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp, Fernando Moraes	A high abstraction, high accuracy power estimation model for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	high abstraction modeling, networks-on-chip, power modeling
1	Leonel Tedesco, Fabien Clermidy, Fernando Moraes	A path-load based adaptive routing algorithm for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	quality of service, networks on chip, dynamic routing, traffic monitoring
1	Guilherme Guindani, Cezar Reinbrecht, Thiago R. da Rosa, Fernando Moraes	Increasing NoC power estimation accuracy through a rate-based model.	NOCS	2009	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Fabien Clermidy, Fernando Moraes	A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	QoS, networks on chip, dynamic routing, traffic monitoring
1	César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Comparison of network-on-chip mapping algorithms targeting low energy consumption.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Everton Carara, Fernando Gehm Moraes	Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes	NoC Power Estimation at the RTL Abstraction Level.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans	MOTIM: an industrial application using nocs.	SBCCI	2008	DBLP DOI BibTeX RDF	ethernet switch, FPGA, prototyping, networks on chip
1	Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi	A simplified executable model to evaluate latency and throughput of networks-on-chip.	SBCCI	2008	DBLP DOI BibTeX RDF	performance evaluation, modeling, networks-on-chip
1	Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner	Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes	Validation of executable application models mapped onto network-on-chip platforms.	SIES	2008	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture	CoRR	2007	DBLP BibTeX RDF
1	César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel	Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique	CoRR	2007	DBLP BibTeX RDF
1	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Inserting Data Encoding Techniques into NoC-Based Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Architectural Issues in Homogeneous NoC-Based MPSoC.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Gilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.	FCCM	2007	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes	Evaluation of Algorithms for Low Energy Mapping onto NoCs.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip	CoRR	2007	DBLP BibTeX RDF
1	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes	Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.	IET Computers & Digital Techniques	2007	DBLP BibTeX RDF
1	Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes	MOTIM - A Scalable Architecture for Ethernet Switches.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Luis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes	SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Everton Carara, Aline Mello, Fernando Moraes	Communication Models in Networks-on-Chip.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, Ney Calazans, Fernando Moraes	Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Fernando Moraes, Ney Calazans	Buffer sizing for QoS flows in wormhole packet switching NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	quality of service, networks on chip, traffic modeling, buffer sizing
1	Everton Carara, Fernando Moraes, Ney Calazans	Router architecture for high-performance NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	session layer, switching modes, networks on chip, virtual channels
1	Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Moraes	A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes	DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.	VTS	2007	DBLP DOI BibTeX RDF
1	Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans	SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.	ICCD	2007	DBLP DOI BibTeX RDF
1	Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes	A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.	ReCoSoC	2007	DBLP BibTeX RDF
1	Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes	A Leak Resistant Architecture Against Side Channel Attacks.	FPL	2006	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes	Application driven traffic modeling for NoCs.	SBCCI	2006	DBLP DOI BibTeX RDF	QoS, applications, networks on chip, traffic modeling
1	Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes	Reconfigurable Systems Enabled by a Network-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
1	Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes	Infrastructure for dynamic reconfigurable systems: choices and trade-offs.	SBCCI	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, NoCs, configuration controllers
1	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes	Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Eduardo Wenzel Brião, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	A scalable test strategy for network-on-chip routers.	ITC	2005	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin	Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.	SBCCI	2005	DBLP DOI BibTeX RDF	traffic effect, networks-on-chip, energy estimation, application mapping
1	César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis	Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes	Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans	MAIA: a framework for networks on chip generation and verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel	Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.	DATE	2005	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.	DATE	2005	DBLP DOI BibTeX RDF
1	Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes	Traffic generation and performance evaluation for mesh-based NoCs.	SBCCI	2005	DBLP DOI BibTeX RDF	performance evaluation, networks on chip, traffic modeling
1	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes	Current mask generation: a transistor level security against DPA attacks.	SBCCI	2005	DBLP DOI BibTeX RDF	cryptography, side channel attacks, DPA, countermeasures
1	Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes	Virtual channels in networks on chip: implementation and evaluation on hermes NoC.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, network-on-chip, virtual channel
1	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes	A new hardware countermeasure for masking power signatures of crypto cores.	ReCoSoC	2005	DBLP BibTeX RDF
1	Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost	HERMES: an infrastructure for low area overhead packet-switching networks on chip.	Integration	2004	DBLP DOI BibTeX RDF
1	Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato	FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.	FPL	2004	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	Reducing test time with processor reuse in network-on-chip based systems.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
1	Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
1	Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes	PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.	SBCCI	2004	DBLP DOI BibTeX RDF	dynamically and partially reconfigurable systems, partial bitstream generation, reconfiguration control, run-time reconfiguration
1	Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes	Propose of a Hardware Implementation for Fingerprint Systems.	FPL	2003	DBLP DOI BibTeX RDF
1	Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans	A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes	Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert	Are coarse grain reconfigurable architectures suitable for cryptography?	VLSI-SOC	2003	DBLP BibTeX RDF
1	Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans	Remote and Partial Reconfiguration of FPGAs: Tools and Trends.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes	Design of a fingerprint system using a hardware/software environment.	FPGA	2003	DBLP DOI BibTeX RDF
1	Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans	Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.	DATE	2003	DBLP DOI BibTeX RDF
1	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
1	Sandro Ferreira, Felipe Haffner, Luis Fernando Pereira, Fernando Moraes	Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Luigi Carro, Edgard de Faria Corrêa, R. Cardozo, Fernando Moraes, Sergio Bampi	Exploiting reconfigurability for low-power control of embedded processors.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli	Projeto para Prototipação de um IP Soft Core MAC Ethernet.	RITA	2001	DBLP BibTeX RDF
1	Fernando Moraes, Michel Robert, Daniel Auvergne	A Virtual CMOS Library Approach for East Layout Synthesis.	VLSI	1999	DBLP BibTeX RDF
1	Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne	Influence of Locig Block Layout Architecture on FPGA Performance.	FPL	1994	DBLP DOI BibTeX RDF

Publications of Fernando Moraes Fernando Gehm Moraes ( http://dblp.L3S.de/Authors/Fernando_Moraes )