Search results for "FinFETs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak	Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Anish Muttreja, Niket Agarwal, Niraj K. Jha	CMOS logic design with independent-gate FinFETs.	ICCD	2007	DBLP DOI BibTeX RDF
2	Brian Swahn, Soha Hassoun	METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs.	ISQED	2006	DBLP DOI BibTeX RDF
1	Hsun Li, Meng-Hsueh Chiang	Design issues and insights of multi-fin bulk silicon FinFETs.	ISQED	2012	DBLP DOI BibTeX RDF
1	Masoud Rostami, Kartik Mohanram	Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	P. C. Feijoo, M. Cho, M. Togo, E. San Andrés, G. Groeseneken	Positive bias temperature instabilities on sub-nanometer EOT FinFETs.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Fataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi	On the Potentials of FinFETs for Asynchronous Circuit Design.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Tetsuo Endoh, Koji Sakui, Yukio Yasuda	Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal	Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	B. Lakshmi, R. Srinivasan	Statistical Modelling of ft to Process Parameters in 30 nm Gate Length Finfets	CoRR	2010	DBLP BibTeX RDF
1	Andrew Carlson, Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic	SRAM Read/Write Margin Enhancements Using FinFETs.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	J. E. Conde, Antonio Cerdeira	3D structure simulation and proceeding to extract mobility parameters for FinFETs varying channel length.	CCE	2010	DBLP DOI BibTeX RDF
1	Vaidyanathan Subramanian, Abdelkarim Mercha, Bertrand Parvais, Morin Dehan, Guido Groeseneken, Willy M. C. Sansen, Stefaan Decoutere	Identifying the Bottlenecks to the RF Performance of FinFETs.	VLSI Design	2010	DBLP DOI BibTeX RDF	multiple gate FET, multi-gate FET, RF, FinFET
1	Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta	Device/circuit interactions at 22nm technology node.	DAC	2009	DBLP DOI BibTeX RDF	22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs
1	Kiyoo Itoh	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
1	Mohab Anis	Advanced IC technology - opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
1	Anish Muttreja, Prateek Mishra, Niraj K. Jha	Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Brian Swahn, Soha Hassoun	Electro-Thermal Analysis of Multi-Fin Devices.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Tamer Cakici, Keejong Kim, Kaushik Roy	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
1	Gerhard Knoblinger	Multi-Gate MOSFET Design.	ISQED	2007	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy	Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yiming Li, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
1	Weida Hu, Xiaoshuang Chen, Xuchang Zhou, Zhijue Quan, Wei Lu	Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study.	Microelectronics Journal	2006	DBLP DOI BibTeX RDF
1	Brian Swahn, Soha Hassoun	Gate sizing: finFETs vs 32nm bulk MOSFETs.	DAC	2006	DBLP DOI BibTeX RDF	gate sizing, thermal modeling, FinFET
1	G. Singer, Philippe Magarshack, Dennis Buss, F.-C. Hsu, H.-K. Kang	"The IC nanometer race -- what will it take to win?".	DAC	2006	DBLP DOI BibTeX RDF	hardware
1	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-Gate SOI Devices for Low-Power and High-Performance Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Tsu-Jae King	FinFETs for nanoscale CMOS digital integrated circuits.	ICCAD	2005	DBLP BibTeX RDF
1	Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri	Design and CAD Challenges in sub-90nm CMOS Technologies.	ICCAD	2003	DBLP DOI BibTeX RDF