Search results for "Flavius Gruian"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Junhe Gan, Paul Pop, Flavius Gruian, Jan Madsen	Robust and flexible mapping for real-time distributed applications during the early design phases.	DATE	2012	DBLP BibTeX RDF
1	Junhe Gan, Flavius Gruian, Paul Pop, Jan Madsen	Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Flavius Gruian, Mark Westmijze	Investigating hardware micro-instruction folding in a Java embedded processor.	JTRES	2010	DBLP DOI BibTeX RDF	BlueJEP, bytecode folding, embedded systems, Java processors, Bluespec
1	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
1	Flavius Gruian, Mark Westmijze	BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management.	SYNASC	2007	DBLP DOI BibTeX RDF
1	Flavius Gruian, Mark Westmijze	BlueJEP: a flexible and high-performance Java embedded processor.	JTRES	2007	DBLP DOI BibTeX RDF	embedded systems, Java processor, Bluespec
1	Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic	The SystemJ approach to system-level design.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid	A Scheduler Support Unit for Reactive Microprocessors.	RTCSA	2006	DBLP DOI BibTeX RDF
1	Flavius Gruian, Per Andersson, Krzysztof Kuchcinski, Martin Schoeberl	Automatic generation of application-specific systems based on a micro-programmed Java core.	SAC	2005	DBLP DOI BibTeX RDF	Java, FPGA, system-on-chip, co-design
1	Flavius Gruian, Zoran A. Salcic	Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Flavius Gruian, Krzysztof Kuchcinski	Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time.	ISLPED	2003	DBLP DOI BibTeX RDF	dynamic voltage scaling, real-time scheduling, low energy
1	Flavius Gruian	Hard real-time scheduling for low-energy using stochastic data and DVS processors.	ISLPED	2001	DBLP DOI BibTeX RDF	scheduling, low-energy, hard real-time, RTOS
1	Flavius Gruian, Krzysztof Kuchcinski	LEneS: task scheduling for low-energy systems using variable supply voltage processors.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Flavius Gruian	System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors.	PACS	2000	DBLP DOI BibTeX RDF	system-level design, low energy, variable voltage processors
1	Flavius Gruian, Krzysztof Kuchcinski	Low-Energy Directed Architecture Selection and Task Scheduling for System-Level Design.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Flavius Gruian, Krzysztof Kuchcinski	Operation Binding and Scheduling for Low Power Using Constraint Logic Programming.	EUROMICRO	1998	DBLP DOI BibTeX RDF

Publications of "Flavius Gruian" ( http://dblp.L3S.de/Authors/Flavius_Gruian )