Search results for "Floorplanning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Jianzhong Shi, Akash Randhar, Dinesh Bhatia	Macro Block Based FPGA Floorplanning.	VLSI Design	1997	DBLP DOI BibTeX RDF	macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design
4	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
3	Bo-Shiun Wu, Tsung-Yi Ho	Bus-pin-aware bus-driven floorplanning.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus planning, floorplanning
3	David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii	Thermal-aware floorplanning exploration for 3D multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	3D, floorplanning, MPSoC, temperature
3	De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang	Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	wire bonding, floorplanning, system-in-package
3	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	T-trees: A tree-based representation for temporal and three-dimensional floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
3	Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.	ISPD	2009	DBLP DOI BibTeX RDF	multiple-supply voltage designs, physical design, floorplanning, vlsi
3	Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han	A Parallel Simulated Annealing Approach for Floorplanning in VLSI.	ICA3PP	2009	DBLP DOI BibTeX RDF	FFA, Parallel Computing, Simulated Annealing, OpenMP, Floorplanning
3	Jinzhu Chen, Guolong Chen, Wenzhong Guo	A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning.	ISICA	2009	DBLP DOI BibTeX RDF	discrete PSO, MOP, floorplanning
3	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	A nonlinear optimization methodology for VLSI fixed-outline floorplanning.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming
3	Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng	Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.	ISPD	2008	DBLP DOI BibTeX RDF	crosstalk reduction, full-chip routing, gridless routing, implicit connection graph-based router, non-slicing floorplanning, detailed routing
3	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Temporal floorplanning using the three-dimensional transitive closure subGraph.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
3	Song Chen, Takeshi Yoshimura	A stable fixed-outline floorplanning method.	ISPD	2007	DBLP DOI BibTeX RDF	floorplanning, sequence pair, fixed-outline
3	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani	Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	floorplanning, thermal, 3D IC
3	Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, transient analysis
3	Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani	How does partitioning matter for 3D floorplanning?	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	partitioning, floorplanning, 3D IC, wire length
3	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Integrating dynamic thermal via planning with 3D floorplanning algorithm.	ISPD	2006	DBLP DOI BibTeX RDF	3D floorplanning, thermal optimization, thermal via
3	Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu	Optimal cell flipping in placement and floorplanning.	DAC	2006	DBLP DOI BibTeX RDF	flipping, placement, floorplanning, orientation, wirelength
3	Meng-Chiou Wu, Rung-Bin Lin	Reticle floorplanning of flexible chips for multi-project wafers.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	mask cost, multi-project wafer, reticle floorplanning, dicing
3	Rong Liu, Sheqin Dong, Xianlong Hong	Fixed-outline floorplanning based on common subsequence.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	common subsequence, floorplanning, fixed-outline
3	Tung-Chieh Chen, Yao-Wen Chang	Modern floorplanning based on fast simulated annealing.	ISPD	2005	DBLP DOI BibTeX RDF	simulated annealing, floorplanning
3	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	ISPD	2005	DBLP DOI BibTeX RDF	bus planning, floorplanning, VLSI CAD
3	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
3	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
3	Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl	An area-optimality study of floorplanning.	ISPD	2004	DBLP DOI BibTeX RDF	area partitioning, block packing, optimality, benchmarking, placement, floorplanning, aspect ratios
3	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floorplanning for deep submicron processor design.	DAC	2004	DBLP DOI BibTeX RDF	microarchitectural planning, computer architecture, floorplanning
3	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.	DAC	2004	DBLP DOI BibTeX RDF	piecewise-linear, performance, pipeline, interconnect, floorplanning
3	Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang	Constrained "Modern" Floorplanning.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, network flow, rectilinear polygons
3	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu	An integrated floorplanning with an efficient buffer planning algorithm.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, buffer insertion, routability
3	Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang	Multilevel floorplanning/placement for large-scale modules using B*-trees.	DAC	2003	DBLP DOI BibTeX RDF	multilevel framework, floorplanning, lagrangian relaxation
3	Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang	Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	Interconnect-Driven Floorplanning, Performance Optimization
3	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani	Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.	ISPD	2002	DBLP DOI BibTeX RDF	floorplanning, routability, interconnect estimation
3	Xiaoping Tang, D. F. Wong	Floorplanning with alignment and performance constraints.	DAC	2002	DBLP DOI BibTeX RDF	floorplanning, longest common subsequence, sequence pair
3	Jingcao Hu, Yangdong Deng, Radu Marculescu	System-Level Point-to-Point Communication Synthesis using Floorplanning Information.	VLSI Design	2002	DBLP DOI BibTeX RDF	System-leve design, low-power, floorplanning, Communication synthesis, point-to-point communication
3	Swanwa Liao, Mario A. Lopez, Dinesh P. Mehta	Constrained polygon transformations for incremental floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	floorplanning, incremental design, rectilinear polygons
3	Israel Koren, Zahava Koren	Incorporating Yield Enhancement into the Floorplanning Process.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
3	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	3-D floorplanning, Reconfigurable computing, floorplanning
3	Pradeep Prabhakaran, Prithviraj Banerjee	Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis.	VLSI Design	1998	DBLP DOI BibTeX RDF	timing driven synthesis, High-level synthesis, floorplanning
3	Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin	Delay bounded buffered tree construction for timing driven floorplanning.	ICCAD	1997	DBLP DOI BibTeX RDF	Total Wire Length, DBB-tree, SPT, Floorplanning, Buffer Insertion, Delay Bounds, Elmore Delay, MST
3	Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe	Hybrid floorplanning based on partial clustering and module restructuring.	ICCAD	1996	DBLP DOI BibTeX RDF	slicing structure, clustering, placement, floorplanning
3	Susmita Sur-Kolay, Bhargab B. Bhattacharya	Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning.	FSTTCS	1988	DBLP DOI BibTeX RDF	plane triangulated graphs, rectangular duals, slicing structures, algorithms, floorplanning, VLSI layout
2	Cristiana Bolchini, Antonio Miele, Chiara Sandionigi	Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.	FPL	2011	DBLP DOI BibTeX RDF	FPGA, floorplanning, partial reconfiguration
2	Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden	An effective approach for large scale floorplanning.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	placement, floorplanning, legalization
2	Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang	Buffer/flip-flop block planning for power-integrity-driven floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
2	Song Chen, Zheng Xu, Takeshi Yoshimura	A generalized V-shaped multilevel method for large scale floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
2	Renshen Wang, Chung-Kuan Cheng	On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	3-D integrated circuits, cuboidal dual, computational complexity
2	Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen	Voltage-island driven floorplanning considering level-shifter positions.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island
2	Cheng-Yu Wang, Wai-Kei Mak	Signal skew aware floorplanning and bumper signal assignment technique for flip-chip.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Jia Wang, Hai Zhou	Exploring adjacency in floorplanning.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay	Floorplanning for Partial Reconfiguration in FPGAs.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	Handling complexities in modern large-scale mixed-size placement.	DAC	2009	DBLP DOI BibTeX RDF	incremental placement, mixed-size design, floorplanning
2	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou	Optimizing wirelength and routability by searching alternative packings in floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	wirelength reduction, Floorplanning
2	Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin	A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Song Chen, Takeshi Yoshimura	Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Minsik Cho, David Z. Pan	Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Tsu-Shuan Chang, Manish Kumar, Teng-Sheng Moh, Chung-Li Tseng	On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem.	ISQED	2008	DBLP DOI BibTeX RDF
2	Tilen Ma, Evangeline F. Y. Young	TCG-based multi-bend bus driven floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Chaomin Luo, Miguel F. Anjos, Anthony Vannelli	Large-scale fixed-outline floorplanning design using convex optimization techniques.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Dae Hyun Kim, Sung Kyu Lim	Bus-aware microarchitectural floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Pradeep Fernando, Srinivas Katkoori	An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Hushrav Mogal, Kia Bazargan	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Qiang Ma 0002, Evangeline F. Y. Young	Network flow-based power optimization under timing constraints in MSV-driven floorplanning.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Mark Po-Hung Lin, Shyh-Chang Lin	Analog placement based on hierarchical module clustering.	DAC	2008	DBLP DOI BibTeX RDF	analog placement, floorplanning
2	Jackey Z. Yan, Chris Chu	DeFer: deferred decision making enabled fixed-outline floorplanner.	DAC	2008	DBLP DOI BibTeX RDF	deferred decision making, floorplanning, fixed outline
2	Juan C. Quiroz, Amit Banerjee, Sushil J. Louis	IGAP: interactive genetic algorithm peer to peer.	GECCO	2008	DBLP DOI BibTeX RDF	collaboration, peer to peer network, floorplanning, interactive genetic algorithm
2	Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh	Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Maolin Tang, Xin Yao	A Memetic Algorithm for VLSI Floorplanning.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2007	DBLP DOI BibTeX RDF
2	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He	Microarchitecture Configurations and Floorplanning Co-Optimization.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
2	Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong	OPC-Friendly Bus Driven Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
2	Love Singhal, Elaheh Bozorgzadeh	Novel Multi-Layer floorplanning for Heterogeneous FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
2	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
2	Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen	Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu	Floorplanning in Modern FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
2	William H. Kao, Xiaopeng Dong	Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang 0003, Ching-Hwa Cheng	Noise-Aware Floorplanning for Fast Power Supply Network Design.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Qiang Ma 0002, Evangeline F. Y. Young	Voltage island-driven floorplanning.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang	An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Chunta Chu, Xinyi Zhang, Lei He, Tong Jing	Temperature aware microprocessor floorplanning considering application dependent power load.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong	An effective buffer planning algorithm for IP based fixed-outline SOC placement.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline
2	Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat	Floorplan repair using dynamic whitespace management.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning, legalization
2	Chiu-Wing Sham, Evangeline F. Y. Young	Area reduction by deadspace utilization on interconnect optimized floorplan.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	area reduction, Floorplanning
2	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
2	Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong	Minimizing wire length in floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Mario R. Casu, Luca Macchiarulo	Floorplanning With Wire Pipelining in Adaptive Communication Channels.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Tung-Chieh Chen, Yao-Wen Chang	Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Peter G. Sassone, Sung Kyu Lim	Traffic: a novel geometric algorithm for fast wire-optimized floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jia Wang, Hai Zhou, Ping-Chih Wu	Processing Rate Optimization by Sequential System Floorplanning.	ISQED	2006	DBLP DOI BibTeX RDF
2	Love Singhal, Elaheh Bozorgzadeh	Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.	FPL	2006	DBLP DOI BibTeX RDF
2	Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin	Floorplanning Based on Particle Swarm Optimization.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Vijay Sundaresan, Ranga Vemuri	A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Royce L. S. Ching, Evangeline F. Y. Young	Shuttle mask floorplanning with modified alpha-restricted grid.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	multi-project wafers, reticle design
2	Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang	Simultaneous block and I/O buffer floorplanning for flip-chip design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Minsik Cho, Hongjoong Shin, David Z. Pan	Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Yong Zhan, Yan Feng, Sachin S. Sapatnekar	A fixed-die floorplanning algorithm using an analytical approach.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma	A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.	APCCAS	2006	DBLP DOI BibTeX RDF