Search results for "Frank Hannig"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.	ARCS	2012	DBLP DOI BibTeX RDF
1	Sascha Roloff, Frank Hannig, Jürgen Teich	Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich	Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays.	Embedded Systems Letters	2011	DBLP DOI BibTeX RDF
1	Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration.	ARCS	2011	DBLP DOI BibTeX RDF
1	Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau	Resource-aware programming and simulation of MPSoC architectures through extension of X10.	SCOPES	2011	DBLP DOI BibTeX RDF
1	Vahid Lari, Frank Hannig, Jürgen Teich	Distributed Resource Reservation in Massively Parallel Processor Arrays.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich	Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor.	MARC Symposium	2011	DBLP BibTeX RDF
1	Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca (eds.)	22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011	ASAP	2011	DBLP BibTeX RDF
1	Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich	Decentralized dynamic resource management support for massively parallel processor arrays.	ASAP	2011	DBLP DOI BibTeX RDF
1	Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade	Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger	A deeply pipelined and parallel architecture for denoising medical images.	FPT	2010	DBLP DOI BibTeX RDF
1	François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski (eds.)	21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010	ASAP	2010	DBLP BibTeX RDF
1	Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert	Modeling and synthesis of communication subsystems for loop accelerator pipelines.	ASAP	2010	DBLP DOI BibTeX RDF
1	Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig	Compilation techniques for CGRAs: exploring all parallelization approaches.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Frank Hannig	Scheduling Techniques for High-Throughput Loop Accelerators.		2009	RDF
1	Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier	A holistic approach for tightly coupled reconfigurable parallel processors.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich	Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Jürgen Teich	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.	ARCS	2009	DBLP DOI BibTeX RDF
1	Frank Hannig, Hritam Dutta, Jürgen Teich	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.	ARCS	2009	DBLP DOI BibTeX RDF
1	Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich	Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.	ASAP	2009	DBLP DOI BibTeX RDF
1	Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich	Impact of Loop Tiling on the Controller Logic of Acceleration Engines.	ASAP	2009	DBLP DOI BibTeX RDF
1	Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich	Model-based synthesis and optimization of static multi-rate image processing algorithms.	DATE	2009	DBLP BibTeX RDF
1	Vahid Lari, Frank Hannig, Jürgen Teich	System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Coarse-grained reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich	Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.	DSD	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.	FCCM	2008	DBLP DOI BibTeX RDF
1	Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich	PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.	ARC	2008	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich	Efficient control generation for mapping nested loop programs onto processor arrays.	Journal of Systems Architecture	2007	DBLP DOI BibTeX RDF
1	Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement	Modeling of Interconnection Networks in Massively Parallel Processor Architectures.	ARCS	2007	DBLP DOI BibTeX RDF
1	Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet	A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.	ERSA	2007	DBLP BibTeX RDF
1	Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient event-driven simulation of parallel processor architectures.	SCOPES	2007	DBLP DOI BibTeX RDF	embedded tools, simulation, modeling, processor arrays
1	Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier	Massively Parallel Processor Architectures: A Co-design Approach.	ReCoSoC	2007	DBLP BibTeX RDF
1	Frank Hannig, Hritam Dutta, Jürgen Teich	Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology.	IJES	2006	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Jürgen Teich	Controller Synthesis for Mapping Partitioned Programs on Array Architectures.	ARCS	2006	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich	A Generic Framework for Rapid Prototyping of System-on-Chip Designs.	CDES	2006	DBLP BibTeX RDF
1	Hritam Dutta, Frank Hannig, Jürgen Teich	Hierarchical Partitioning for Piecewise Linear Algorithms.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger	A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.	ASAP	2006	DBLP DOI BibTeX RDF
1	Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich	A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.	ReCoSoC	2006	DBLP BibTeX RDF
1	Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich	Defragmenting the Module Layout of a Partially Reconfigurable Device	CoRR	2005	DBLP BibTeX RDF
1	Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich	Automatic FIR Filter Generation for FPGAs.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich	Defragmenting the Module Layout of a Partially Reconfigurable Device.	ERSA	2005	DBLP BibTeX RDF
1	Frank Hannig, Jürgen Teich	Output Serialization for FPGA-based and Coarse-grained Processor Arrays.	ERSA	2005	DBLP BibTeX RDF
1	Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich	Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys	Co-Design of Massively Parallel Embedded Processor Architectures.	ReCoSoC	2005	DBLP BibTeX RDF
1	Alexey Kupriyanov, Frank Hannig, Jürgen Teich	High-Speed Event-Driven RTL Compiled Simulation.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Frank Hannig, Hritam Dutta, Jürgen Teich	Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Frank Hannig, Jürgen Teich	Dynamic Piecewise Linear/Regular Algorithms.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Frank Hannig, Jürgen Teich	Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.	ASAP	2004	DBLP DOI BibTeX RDF
1	Marcus Bednara, Frank Hannig, Jürgen Teich	Generation of Distributed Loop Control.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
1	Frank Hannig, Jürgen Teich	Energy estimation of nested loop programs.	SPAA	2002	DBLP DOI BibTeX RDF	hardware mapping, low power, processor arrays
1	Frank Hannig, Jürgen Teich	Design Space Exploration for Massively Parallel Processor Arrays.	PaCT	2001	DBLP DOI BibTeX RDF

Publications of "Frank Hannig" ( http://dblp.L3S.de/Authors/Frank_Hannig )