Search results for "Fredrik Dahlgren"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Fredrik Dahlgren	Partial Continuous Functions and Admissible Domain Representations.	J. Log. Comput.	2007	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren	Partial Continuous Functions and Admissible Domain Representations.	CiE	2006	DBLP DOI BibTeX RDF	domain representations, computability theory, computable analysis, Domain theory
1	Fredrik Dahlgren	Computability and continuity in metric partial algebras equipped with computability structures.	Math. Log. Q.	2004	DBLP DOI BibTeX RDF
1	Magnus Ekman, Per Stenström, Fredrik Dahlgren	TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF	virtual caches, low-power, CMP, snoop
1	Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec	Topic 08+13: Instruction-Level Parallelism and Computer Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren	Future Mobile Phones--Complex Design Challenges from an Embedded Systems Perspective. (PDF / PS)	ICECCS	2001	DBLP DOI BibTeX RDF
1	Ashley Saulsbury, Fredrik Dahlgren, Per Stenström	Recency-based TLB preloading.	ISCA	2000	DBLP DOI BibTeX RDF
1	Jim Nilsson, Fredrik Dahlgren	Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF
1	Martin Kämpe, Fredrik Dahlgren	Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	cache performance, Spatial locality
1	Magnus Karlsson, Fredrik Dahlgren, Per Stenström	A Prefetching Technique for Irregular Accesses to Linked Data Structures.	HPCA	2000	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren	Techniques for Improving Performance of Hybrid Snooping Cache Protocols.	J. Parallel Distrib. Comput.	1999	DBLP DOI BibTeX RDF
1	Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström	Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors.	J. Parallel Distrib. Comput.	1999	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Josep Torrellas	Cache-Only Memory Architectures.	IEEE Computer	1999	DBLP DOI BibTeX RDF
1	Jim Nilsson, Fredrik Dahlgren	Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors. (PDF / PS)	ICPP	1999	DBLP DOI BibTeX RDF	load-store sequences, performance evaluation, databases, operating systems, multiprocessors, computer architecture, transaction processing, cache coherence protocols
1	Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren	Efficient management of memory hierarchies in embedded DRAM systems.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	cache, latency, memory hierarchy, processor, DRAM, COMA
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	competitive-update protocols, write caches, performance evaluation, prefetching, Shared-memory multiprocessors, cache-coherence protocols
1	Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal	The Sensitivity of Communication Mechanisms to Bandwidth and Latency.	HPCA	1998	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Per Stenström, Mårten Björkman	Reducing the Read-Miss Penalty for Flat COMA Protocols.	Comput. J.	1997	DBLP DOI BibTeX RDF
1	Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois	Boosting the Performance of Shared Memory Multiprocessors.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Anders Landin	Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors.	HPCA	1997	DBLP DOI BibTeX RDF	broken inclusion, memory pressure, replacement traffic, loose inclusion, no inclusion, shared memory, COMA
1	Fredrik Dahlgren, Per Stenström	Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	Hardware-controlled prefetching, relaxed memory consistency, performance evaluation, shared-memory multiprocessors, latency tolerance
1	Per Stenström, Fredrik Dahlgren	Applications for Shared Memory Multiprocessors (Guest Editors' Introduction).	IEEE Computer	1996	DBLP BibTeX RDF
1	Anders Landin, Fredrik Dahlgren	Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	bus-based COMA, standard UMA architecture, program-driven simulation, SPLASH, cache only memory architecture, shared-memory multiprocessors, shared memory systems, memory architecture, cache storage, shared-bus multiprocessors
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Sequential Hardware Prefetching in Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	Hardware-controlled prefetching, sequential prefetching, performance evaluation, shared-memory multiprocessors, memory consistency models, latency tolerance
1	Fredrik Dahlgren, Per Stenström	Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors.	J. Parallel Distrib. Comput.	1995	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren	Boosting the Performance of Hybrid Snooping Cache Protocols.	ISCA	1995	DBLP DOI BibTeX RDF
1	Mårten Björkman, Fredrik Dahlgren, Per Stenström	Using hints to reduce the read miss penalty for flat COMA protocols.	HICSS	1995	DBLP DOI BibTeX RDF	read miss penalty, flat COMA protocols, flat cache-only memory architectures, attraction-memory miss, directory interrogation, network traversals, data copy holder identity tracking, benchmark applications, protocol complexity, performance evaluation, transaction processing, memory architecture, cache storage, performance improvement, hints, architectural simulations, memory protocols
1	Fredrik Dahlgren, Per Stenström	Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.	HPCA	1995	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Combined Performance Gains of Simple Cache Protocol Extensions.	ISCA	1994	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Per Stenström	Reducing the Write Traffic for a Hybrid Cache Protocol.	ICPP	1994	DBLP BibTeX RDF
1	Fredrik Dahlgren, Michel Dubois, Per Stenström	Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors.	ICPP	1993	DBLP BibTeX RDF
1	Fredrik Dahlgren	A program-driven simulation model of an MIMD multiprocessor.	Annual Simulation Symposium	1991	DBLP DOI BibTeX RDF
1	Fredrik Dahlgren, Per Stenström	On Reconfigurable On-Chip Data Caches.	MICRO	1991	DBLP DOI BibTeX RDF
1	Per Stenström, Fredrik Dahlgren, Lars Lundberg	A Lockup-Free Multiprocessor Cache Design.	ICPP	1991	DBLP BibTeX RDF

Publications of "Fredrik Dahlgren" ( http://dblp.L3S.de/Authors/Fredrik_Dahlgren )