| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
Effective Robustness Analysis Using Bounded Model Checking Techniques.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Dehbashi, André Sülflow, Görschwin Fey |
Automated Design Debugging in a Testbench-Based Verification Environment. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey |
Orchestrated multi-level information flow analysis to understand SoCs. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Finder, André Sülflow, Görschwin Fey |
Latency Analysis for Sequential Circuits. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
Soft Error Analysis, f, Debugging, Sequential Circuits, Latency |
| 1 | Görschwin Fey |
Assessing System Vulnerability Using Formal Verification Techniques. |
MEMICS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler |
Automatic property generation for the formal verification of bus bridges. |
DDECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler |
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). |
it - Information Technology |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler |
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
RobuCheck: A Robustness Checker for Digital Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Finder, Görschwin Fey |
Evaluating Debugging Algorithms from a Qualitative Perspective. |
FDL |
2010 |
DBLP BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Rolf Drechsler |
Using QBF to increase accuracy of SAT-based debugging. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Rolf Drechsler |
Towards Unifying Localization and Explanation for Automated Debugging. |
MTV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Görschwin Fey |
Formal verification meets robustness checking - Techniques and challenges. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, Rolf Drechsler |
A better-than-worst-case robustness measure. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler |
Polynomial datapath optimization using constraint solving and formal modelling. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
Advanced verification by automatic property generation. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille |
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). |
it - Information Technology |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille |
Test Pattern Generation using Boolean Proof Engines. |
|
2009 |
DOI RDF |
|
| 1 | André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler |
WoLFram- A Word Level Framework for Formal Verification. |
IEEE International Workshop on Rapid System Prototyping |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey |
Deterministic Algorithms for ATPG under Leakage Constraints. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
Robustness Check for Multiple Faults Using Formal Techniques. |
DSD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, André Sülflow, Rolf Drechsler |
Computing bounds for fault tolerance using formal techniques. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
fault tolerance, formal verification, SAT |
| 1 | André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler |
Evaluation of Cardinality Constraints on SMT-Based Debugging. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler |
Increasing the accuracy of SAT-based debugging. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
On the construction of small fully testable circuits with low depth. |
Microprocessors and Microsystems - Embedded Hardware Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler |
Automatic Fault Localization for Property Checking. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille |
On Acceleration of SAT-Based ATPG for Industrial Designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler |
Robustness and usability in modern design flows. |
|
2008 |
RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler |
A Basis for Formal Robustness Checking. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Formal Methods, Robustness, Fault models, SAT |
| 1 | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
Using unsatisfiable cores to debug multiple design errors. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
sat-based debugging, unsatisfiable core, fault localization |
| 1 | Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke |
Automatic Generation of Complex Properties for Hardware Designs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. |
MEMOCODE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
On the Construction of Small Fully Testable Circuits with Low Depth. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler |
SWORD: A SAT like prover using word level information. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Tim Warode, Rolf Drechsler |
Reusing Learned Information in SAT-based ATPG. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler |
SAT-based ATPG for Path Delay Faults in Sequential Circuits. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Tille, Görschwin Fey, Rolf Drechsler |
Instance Generation for SAT-based ATPG. |
DDECS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler |
Minimizing the number of paths in BDDs: Theory and algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey |
Increasing robustness and usability of circuit design tools by using formal techniques. |
|
2006 |
RDF |
|
| 1 | Görschwin Fey, Junhao Shi, Rolf Drechsler |
Efficiency of Multi-Valued Encoding in SAT-based ATPG. |
ISMVL |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Görschwin Fey |
Automatic Test Pattern Generation. |
SFM |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Görschwin Fey, Sebastian Kinder |
An Integrated Approach for Combining BDD and SAT Provers. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
On the relation between simulation-based and SAT-based diagnosis. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Daniel Große, Rolf Drechsler |
Avoiding false negatives in formal verification for protocol-driven blocks. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler |
Automatic Fault Localization for Property Checking. |
Haifa Verification Conference |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler |
Advanced BDD optimization. |
|
2005 |
DOI RDF |
|
| 1 | Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große |
SyCE: An Integrated Environment for System Design in SystemC. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler |
Utilizing don't care states in SAT-based bounded sequential problems. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
don't care states, unreachable states, satisfiability, bounded model checking, sequential equivalence checking |
| 1 | Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
Controlling the Memory During Manipulation of Word-Level Decision Diagrams. |
ISMVL |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhao Shi, Görschwin Fey, Rolf Drechsler |
Bridging fault testability of BDD circuits. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Junhao Shi, Görschwin Fey |
Synthesis of fully testable circuits from BDDs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler |
Disjoint Sum of Product Minimization by Evolutionary Algorithms. |
EvoWorkshops |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Junhao Shi, Rolf Drechsler |
BDD Circuit Optimization for Path Delay Fault Testability. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski |
Algorithms for Taylor Expansion Diagrams. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler |
Improving simulation-based verification by means of formal methods. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey |
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Görschwin Fey, Rolf Drechsler |
Finding Good Counter-Examples to Aid Design Verification. (PDF / PS) |
MEMOCODE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhao Shi, Görschwin Fey, Rolf Drechsler |
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rolf Drechsler, Junhao Shi, Görschwin Fey |
MuTaTe: an efficient design for testability technique for multiplexor based circuits. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
multiplexor based circuits, design for testability, logic synthesis, BDDs, decision diagrams |
| 1 | Görschwin Fey, Sebastian Kinder, Rolf Drechsler |
Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Große, Görschwin Fey, Rolf Drechsler |
Modeling Multi-Valued Circuits in SystemC. (PDF / PS) |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
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